DATA SHEET URM Search Results
DATA SHEET URM Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| 54HC152J/B |
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54HC152 - 8 to 1 Line Data Selectors/Multiplexers |
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| 54LS298/BEA |
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54LS298 - DATA SEL/MULTIPLEXER, QUAD 2-INPUT, WITH STORAGE - Dual marked (M38510/30909BEA) |
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| 54S153/BEA |
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54S153 - DATA SEL/MULTIPLEXER, DUAL 4-INPUT - Dual marked (M38510/07902BEA) |
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| 54F257/BEA |
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54F257 - DATA SEL/MULTIPLEXER, QUAD 2-INPUT, WITH 3-STATE OUTPUTS - Dual marked (M38510/33906BEA) |
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| 54F257/BFA |
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54F257 - DATA SEL/MULTIPLEXER, QUAD 2-INPUT, WITH 3-STATE OUTPUTS - Dual marked (M38510/33906BFA) |
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DATA SHEET URM Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.4, March 2007 LatticeECP2/M Family Data Sheet Introduction March 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic |
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DS1006 DS1006 200MHz) 266MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. 266MHz. | |
LFE2M20E-5FN256CContextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.8, August 2007 LatticeECP2/M Family Data Sheet Introduction August 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic |
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DS1006 DS1006 200MHz) 266MHz) ECP2M50 484/672/900-fpBGA) ECP2M70 900-fpBGA ECP2M100 900-fpBGA) LFE2M20E-5FN256C | |
T 4148
Abstract: PR65A
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DS1006 DS1006 200MHz) 266MHz) ECP2M50 484/672/900-fpBGA) ECP2M70 900-fpBGA ECP2M100 900-fpBGA) T 4148 PR65A | |
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Contextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.2, December 2006 LatticeECP2/M Family Data Sheet Introduction December 2006 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic |
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DS1006 DS1006 200MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. | |
LFE2-20E-5FN256I
Abstract: lfe2m35e-7fn484c LFE2M50E-5F484C LFE2M50E-5FN484C LFE2M50E5F484C lfe2m35e7fn484c LFE2M50E-6FN484C
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DS1006 DS1006 200MHz) LFE2-12E 256fpBGA 484-fpBGA ECP2M35E. LFE2-20E-5FN256I lfe2m35e-7fn484c LFE2M50E-5F484C LFE2M50E-5FN484C LFE2M50E5F484C lfe2m35e7fn484c LFE2M50E-6FN484C | |
TBA 931Contextual Info: LatticeECP2 Family Data Sheet DS1006 Version 01.1, August 2006 LatticeECP2 Family Data Sheet Introduction August 2006 Advance Data Sheet DS1006 Features • Dedicated gearing logic • Source synchronous standards support – SPI4.2, SFI4, XGMII – High Speed ADC/DAC devices |
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DS1006 DS1006 18x18 36x36 200MHz) 33/25/1attice ECP2-12. TBA 931 | |
6H5n-1
Abstract: LFXP10C-3F256I lfxp10c3 LFXP20C-5F256C lfxp15c-4f256 LFXP10C-4F256I LFXP6C-5F256C LFXP20C-4F256C lfxp10c-3 lfxp15c-4
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HSTL15 TN1052) TN1082) 6H5n-1 LFXP10C-3F256I lfxp10c3 LFXP20C-5F256C lfxp15c-4f256 LFXP10C-4F256I LFXP6C-5F256C LFXP20C-4F256C lfxp10c-3 lfxp15c-4 | |
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Contextual Info: LatticeXP Family Data Sheet Version 03.0, September 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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HSTL15 TN1050) TN1052) TN1082) | |
Lattice Semiconductor Package Diagrams 256-Ball fpBGA
Abstract: 16-bit adder
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DS1007 DS1007 200MHz) ECP2-12. Lattice Semiconductor Package Diagrams 256-Ball fpBGA 16-bit adder | |
lfe2
Abstract: PL25B
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DS1006 DS1006 200MHz) 266MHz) 256fpBGA 484-fpBGA ECP2M35E. 266MHz. 1152-fpBGA ECP2M70 lfe2 PL25B | |
16X4
Abstract: PR72A
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200MHz) 18x18 36x36 55Kbits 1032Kbi4) TN1105) TN1106) TN1107) 16X4 PR72A | |
PR88AContextual Info: LatticeECP2/M Family Data Sheet DS1006 Version 02.5, March 2007 LatticeECP2/M Family Data Sheet Introduction March 2007 Advance Data Sheet DS1006 • Pre-Engineered Source Synchronous I/O Features • DDR registers in I/O cells • Dedicated gearing logic |
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DS1006 DS1006 200MHz) 266MHz) Rapid007 256fpBGA 484-fpBGA ECP2M35E. 266MHz. PR88A | |
PR4BContextual Info: LatticeXP Family Data Sheet Version 01.1, April 2005 LatticeXP Family Data Sheet Introduction February 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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HSTL15 TN1052) TN1082) PR4B | |
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Contextual Info: LatticeXP Family Data Sheet Version 04.0, December 2005 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL |
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HSTL15 TN1050) TN1052) TN1082) | |
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Contextual Info: LatticeXP Family Data Sheet Version 02.0, July 2005 LatticeXP Family Data Sheet Introduction July 2005 Advance Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL |
Original |
HSTL15 TN1052) TN1082) | |
LFXP6C-4FN256C
Abstract: LFXP6C-3FN256I LFXP LFXP10C-3F256I LFXP3C 5TN100C DDR333 LFXP10 LVCMOS25 LVCMOS33 LFXP3C-3TN144C
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DS1001 DS1001 HSTL15 LVDS25E LFXP6C-4FN256C LFXP6C-3FN256I LFXP LFXP10C-3F256I LFXP3C 5TN100C DDR333 LFXP10 LVCMOS25 LVCMOS33 LFXP3C-3TN144C | |
PT15BContextual Info: LatticeXP Family Data Sheet Version 04.1, February 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL |
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HSTL15 1000x TN1051) TN1050) TN1052) TN1082) PT15B | |
LFXP20C-4F484CContextual Info: LatticeXP Family Data Sheet DS1001 Version 04.6, June 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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DS1001 DS1001 HSTL15 1000x LVDS25E LFXP20C-4F484C | |
PT15BContextual Info: LatticeXP Family Data Sheet DS1001 Version 04.8, December 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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DS1001 DS1001 HSTL15 1000x LVDS25E PT15B | |
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Contextual Info: LatticeXP Family Data Sheet Version 01.2, May 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I |
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HSTL15 TN1052) TN1082) | |
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Contextual Info: LatticeXP Family Data Sheet Version 01.3, June 2005 LatticeXP Family Data Sheet Introduction May 2005 Advance Data Sheet Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 − LVTTL – SSTL 18 Class I |
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HSTL15 TN1052) TN1082) | |
LFXP10C-4FN256C
Abstract: PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C
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HSTL15 1000x TN1051) TN1050) TN1052) TN1082) LFXP10C-4FN256C PB27A PT15B LFXP15C-5FN388C LFXP10C5FN256C LFXP3C-3QN208C LFXP6C-5FN256C LFXP10C-4FN388C LFXP6C-5TN144C LFXP20C-5FN484C | |
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Contextual Info: LatticeXP Family Data Sheet DS1001 Version 04.7, August 2006 LatticeXP Family Data Sheet Introduction December 2005 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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DS1001 DS1001 HSTL15 LVDS25E | |
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Contextual Info: LatticeXP Family Data Sheet DS1001 Version 05.0, July 2007 LatticeXP Family Data Sheet Introduction July 2007 Data Sheet DS1001 • Flexible I/O Buffer Features • Programmable sysIO buffer supports wide range of interfaces: − LVCMOS 3.3/2.5/1.8/1.5/1.2 |
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DS1001 DS1001 HSTL15 1000x | |