D917 Search Results

IS61QDB22M36

Abstract: D0-35 IS61QDB24M18
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 2) Synchronous SRAMs . A May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Two echo clocks (CQ and CQ) that are delivered

IS61DDB21M36

Abstract: 61DDB22M18 IS61DDB22M18-300M3L IS61DDB22M18 IS61DDB22M18-250M3LI
Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . I May 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

D0-35

Abstract: IS61QDB42M36 IS61QDB42M36-300M3 IS61QDB44M18 IS61QDB44M18-300M3
Contextual Info: 72 Mb 2M x 36 & 4M x 18 QUAD (Burst of 4) Synchronous SRAMs 7 Q . May 2009 Features • 2M x 36 or 4M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

IS61QDB41M36

Abstract: 61QDB41M36 IS61QDB41M36-250M3L D0-35 IS61QDB41M36-250M3 IS61QDB42M18
Contextual Info: 36 Mb 1M x 36 & 2M x 18 QUAD (Burst of 4) Synchronous SRAMs . I April 2009 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Separate read and write ports with concurrent read and write operations. • Synchronous pipeline read with late write operation.

D018

Abstract: D019 D032
Contextual Info: TOSHIBA THMY51E10C70,75,80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY51E10C is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59SM804CFT DRAMs and PLL/Registers on a printed circuit board.

D018

Abstract: D019 D032 D051 THMY51E10B70
Contextual Info: T O S H IB A THMY51E10B70,75,80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY51E10B is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59SM804BFT DRAMs and PLL/Registers on a printed circuit board.

Contextual Info: T O S H IB A THMY25E10A70,75,80 TENTATIVE T O S H IB A H Y B R ID D IG ITA L IN T EG R A T ED C IRCUIT 33,554,432-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY25E10A is a 33,554,432-word by 72-bit synchronous dynamic RAM module consisting of

Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation

Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE

OQ45

Abstract: D018 D019 D032
Contextual Info: TOSHIBA THMY7216D0CEG-75,-80 TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT TENTATIVE 16,777,216-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7216D0CEG is a 16,777,216-word by 72-bit synchronous dynamic RAM module consisting of 18 TC59S6404CFT DRAMs and PLL/Registers on a printed circuit board.

ra2b

Contextual Info: TOSHIBA THMY7264E0LEG-75,-80 TENTATIVE TOSHIBA HYBRID DIGITAL INTEGRATED CIRCUIT 67,108,864-WORD BY 72-BIT SYNCHRONOUS DRAM MODULE DESCRIPTION The THMY7264E0LEG is a 67,108,864-word by 72-bit synchronous dynamic RAM module consisting of 36 TC59SM704FT DRAMs and PLL/Registers on a printed circuit board.

Contextual Info: IS61DDP2B22M18A IS61DDP2B21M36A 2Mx18, 1Mx36 36Mb DDR-IIP Burst 2 CIO Synchronous SRAM (2.0 Cycle Read Latency) FEATURES •                   1Mx36 and 2Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDP2B41M18A IS61QDP2B451236A 1Mx18 , 512Kx36 18Mb QUAD-P Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                    512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61QDB41M18A IS61QDB451236A 1Mx18, 512Kx36 18Mb QUAD Burst 4 SYNCHRONOUS SRAM FEATURES •                   512Kx36 and 1Mx18 configuration available. On-chip delay-locked loop (DLL) for wide data valid

Contextual Info: IS61DDP2B44M18A/A1/A2 IS61DDP2B42M36A/A1/A2 4Mx18, 2Mx36 72Mb DDR-IIP Burst 4 CIO SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     2Mx36 and 4Mx18 configuration available.

Contextual Info: IS61QDP2B41M18A/A1/A2 IS61QDP2B451236A/A1/A2 1Mx18 , 512Kx36 18Mb QUADP Burst 4 SYNCHRONOUS SRAM (2.0 Cycle Read Latency) FEATURES •                     512Kx36 and 1Mx18 configuration available.

Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb2 SRAM 9Mb QDR SRAM MT54V512H18A 2-Word Burst FEATURES 165-Pin FBGA • 9Mb Density 512K x 18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE

BW35

Contextual Info: ADVANCE‡ 4 MEG X 8, 4 MEG X 9, 2 MEG X 18, 1 MEG X 36 1.8V VDD, HSTL, DDRIIb4 SRAM 36Mb DDRII CIO SRAM 4-WORD BURST MT57W4MH8J MT57W4MH9J MT57W2MH18J MT57W1MH36J FEATURES • • • • • • • • • • • • • • • Figure 1 165-Ball FBGA

Contextual Info: PRELIMINARY‡ 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDR SIO SRAM 18Mb DDR SIO SRAM 2-WORD BURST MT57W2MH8C MT57W1MH18C MT57W512H36C FEATURES • • • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement

Contextual Info: ADVANCE 512K x 18 2.5V VDD, HSTL, QDRb4 SRAM 9Mb QDR SRAM MT54V512H18E 4-Word Burst FEATURES • 9Mb Density 512Kx18 • Separate independent read and write data ports with concurrent transactions • 100% bus utilization DDR READ and WRITE operation

Contextual Info: 36 Mb 1M x 36 & 2M x 18 DDR-II (Burst of 2) CIO Synchronous SRAMs . ISSI March 2005 Features • 1M x 36 or 2M x 18. • On-chip delay-locked loop (DLL) for wide data valid window. • Common data input/output bus. • Synchronous pipeline read with self-timed late

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, QDRb2 SRAM 36Mb QDR SRAM 2-WORD BURST MT54V2MH18A MT54V1MH36A Features Figure 1: 165-Ball FBGA • Separate independent read and write data ports with concurrent transactions • 100 percent bus utilization DDR READ and WRITE

Contextual Info: ADVANCE‡ Die Revision A 2 MEG x 18, 1 MEG x 36 2.5V VDD, HSTL, Pipelined DDRb2 SRAM 36Mb DDR SRAM 2-Word Burst MT57V2MH18A MT57V1MH36A Features • • • • • • • • • • • • • • • • • Figure 1: 165-Ball FBGA Fast cycle times Pipelined, double data rate operation

Contextual Info: 2 MEG X 8, 1 MEG X 18, 512K X 36 1.8V VDD, HSTL, DDRIIb2 SRAM 18Mb DDRII CIO SRAM 2-Word Burst MT57W2MH8B MT57W1MH18B MT57W512H36B FEATURES • • • • • • • • • • • • • • • • DLL circuitry for accurate output data placement Pipelined, double-data rate operation