D74HC Search Results

Contextual Info: ASSESS? D74HC354, D74HCT354 High Speed CMOS Logic 8-lnput Multiplexer/Register, Three-State November 1997 Features Description • C D74HC/HCT354 The Harris D74HC354 and D74HCT354 are data selectors/multiplexers that select one of eight sources. In both

74HC FAMILY

Abstract: elmos TMD54HC373 TMD54HC374 TMD74HC373 TMD74HC374
Contextual Info: TM D54HC 373/TM D74HC 373 3 STATE OCTAL LATCHES TM D54HC 374/TM D74HC 374 TELMOS INC. 3 STATE OCTAL D-FLIP-FLO PS • • • • • • • • CMOS INPUT COMPATIBLE 13 NS PROPAGATION DELAY TYP. 1 ^A MAX. INPUT CURRENT DRIVES 30 LS-TTL LOADS FULL PARALLEL LOAD ACCESS

Contextual Info: D74HCT374 D74HCT534 These # Octal D-type Flip-Flops with 3-state outputs # Octal D-type Flip-Flops (with inverted 3-state outputs; devices are positive edge triggered flip-flops. The • p in a r r a n g e m e n t difference between H D74HCT374 and HD 74H CT534 is only

Contextual Info: D74HC688 18-bit Magnitude Comparator The H D74HC688 compares bit for bit two 8-bit wordt and indicates whether or not they are equal. The P-Q output indfcates equality when it it low. A single active low enable is provided to facilitate cascading of several package* and enable comparison of words greater

Contextual Info: D74HC4060 # 14-stage Binary Counter The HD 74HC 4060 is a 14 stage counter, this device incre- | I PIN ARRANGEMENT ments on the falling edge negative transition} of the input clock, and all their outputs are reset to a low level by apply­ ing a logical high on their reset input. The H D74HC4060

Contextual Info: # 16-bit A d d re ss Com parator The H D74HC678 address com parator sim plifies addressing o f | mem ory boards and /o r other peripheral devices. The fo u r P inputs are norm ally hard w ired w ith PIN ARRANGEMENT a preprogammed F L_ [7 T n Ü J g A‘ U

Contextual Info: D74HCT137 * 3-to-8-line Decoder/Dem ultiplexer w ith Address Latch The H D74HCT137 implements a three-to-eight line decoder | w ith latches on the three address inputs. When G L goes from PIN ARRANGEMENT low to high, the address present at the select inputs A , B and

D74HC

Contextual Info: D74HCT238 3-to-8-line D e co d e r/D e m u ltip le xe r The H D74HC T238 has 3 binary select inputs A, B, and C . | If the device is enabled these inputs determ ined which one of PIN ARRANGEMENT the eight norm ally high o utputs w ill go lo w . T w o active low

Contextual Info: D74HCT374 D74HCT534 # Octal D-type Flip-Flops with 3-state outputs # Octal D-type Flip-Flops (with inverted 3-state outputs) These devices are positive edge triggered flip-flops. The I PIN ARRANGEMENT difference between H D74HC T374 and H D 74H C T534 is only

74HC4518

Contextual Info: D74HC4518 D74HC4520 # Dual BCD Up Counters # Dual Binary Up Counters The H D74HC4518 dual BCD counter and the D74HC4520 dual binary counter consist o f tw o identical, independent, • PIN ARRANGEMENT in te rn a lly synchronous 4-stage counters. The counter stages

Contextual Info: D74HCT564 D74HCT574 # O ctal D-type Flip-Flops w ith 3 -s ta te outputs These devices are positive edge triggered flip -flop s. The d if­ ference between HD74H CT564 and H D74HCT574 is on ly • PIN ARRANGEMENT that the form er has inverting o utputs and the la tte r has non­

74hct family

Abstract: 74HCT TMD54HCT373 TMD54HCT374 TMD74HCT373 TMD74HCT374 373HCT Telmos
Contextual Info: TM D54HCT373/TM D74HCT373 3 STATE OCTAL LATCHES TELIVI OS INC. TM D54HCT374/TM D74HCT374 3 STATE OCTAL D-FLIP-FLOPS Features W hen the LATCH ENABLE input of the 3 7 3 H C T series is high, the Q outputs will follow the D inputs. W hen the LATCH ENABLE goes low, data at the D

D74HC244

Contextual Info: H D 74H C 244 # Octal Buffers/U ne Drivers/Line Receivers with noninverted The H D74HC244 is a non-inverting buffer and has two active low enables (1G and 2G . Each enable independently con­ trols 4 buffers. | PIN ARR A N G EM EN T ig Q E E E E JÄ4 E E

Contextual Info: # 3-to-8-line D e co d er/D e m u ltip lexe r w ith A d d re ss L a tc h The H D74HCT237 decodes a three-bit Address to one-of- | eight active-high outputs. The device has a transparent latch F fo r storage o f the Address. T w o Chip Selects, one active-low

Contextual Info: H D 74H C 244 # Octal B u ffe rs /L in e D riv e rs / L in e Receivers with noninverted 3-state outputs The H D74HC244 is a non-inverting buffer and has two active | PIN ARRANG EMENT low enables (1G and 2G). Each enable independently con­ •È trols 4 buffers.

HD74HC126

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM TS DËJ 0010377 HD7 4 HC12 5 , HD7 4 HC126 * 92D 10377 • PIN ARRANGEMENT The D74HC125, H D74HC126 require the 3-state control input C to be taken high to put the output into the high im­ • pedance condition, whereas the D74HC125, D74HC126

D74HC583

Contextual Info: D74HC583 Semiconductor High Speed CMOS Logic 4-Bit BCD Full Adder With Fast Carry December 1997 Features Description • Adds Two Decimal Numbers The Harris D74HC583 Binary Coded Decimal BCD full adders that add two 4-bit BCD numbers and generate a carry-out bit if the sum exceeds 9.

HD74HC373

Contextual Info: D74HC373 D74HC533 W hen th e la tch enable in p u t • Octal D-type Transparent Latches with 3-state outputs • Octal D-type Transparent Latches (with inverted 3-state outputs) i t h ig h , th e Q o u tp u ts o f | I PIN ARRANGEMENT 1 IH D74HC373 H D 7 4 H C 3 7 3 w ill fo llo w th e O in p u ts a n d th e Q o u tp u ts o f

D74HC109

Contextual Info: HARRIS s e m ic o n d u c to r C D 74H C 109, C D 74H C T 10 9 Dual J -K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 Features • Description Asynchronous Set and Reset The Harris C D74HC109 and C D 74H C T109 are dual J-K flipflops with set and reset. The flip-flop changes state with the

TTP-20DA

Abstract: D74HC
Contextual Info: Package Information In th« HD74AC, HC series of CMOS logic, either of plastic • Package code ol CMOS Logic DIP and small outline packages can be selected. For your ordering, please refer to the following package code. D74HC XXXX P ' I Package code P : Plastic DIP, FP

HD74HC240

Contextual Info: D74HC240 • O ctal B u ffe rs /L in e D r iv e r s /L in e R e c e iv e rs w ith in v e rte d 3 -s t a te o u tp u ts The H D74HC240 is an inverting buffer and has two active | PIN ARRANGEMENT low enables (1G and 2G). Each enable independently con­ —

Contextual Info: H I T A C H I ^ L O G I C / A R R A Y S / M E M TS D E j 44Tb2D3 DDlGblO 92D D74HC4040 # 10610 T - H 5 ~ 3 3 - n 12-stage Binary Counter The D74HC4040 is a 12 stage counter. This device is incre- | D PIN ARRANGEMENT merited on the falling edge negative transition} of the input

Contextual Info: HITACHI/ L O G I C / A R R A Y S / M E M 12 D74HC157 D74HC158 B E I 4iHbaG3 0P104CI3 1 | ~ . 92D 1 04 03 D 7 ^ 7 -.2 /-£ / # Quad. 2-to-1-line Data Selectors/Multiplexers with noninverted outputs # Quad. 2-to-l-line Data Selectors/Multiplexers (with inverted outputs)

74HC50

Contextual Info: Technical Data CD54/74HC354, CD54/74HCT354 CD54/74HC356, CD54/74HCT356 File N u m b e r 1690 Texas . High-Speed CMOS Logic In str u m e n t s Data sheet acquired from Harris Sem iconductor 8-Input Multiplexer/Register, 3-State CD54/74HC/HCT354 — Transparent Data & Select Latches