D5510 Search Results

18E-4-80

Abstract: payne 18ez control schematic scr controls schematic payne 18D 18E-SW 18EZ-4-450 5299s PAYNE Potentiometer 75K 18D-1-10I 18D-4-80SW2 temperature control schematics payne Model 18D
Contextual Info: LIST PRICE SCHEDULE PC-6 Effective date 9/1/2007 SCR POWER CONTROLS Variable Voltage Controls • • Phase Angle Zero Fired On/Off Controls Product Range • • • • 120 to 600 VAC 10-1200 Amps Manual or Automatic Control Open or Enclosed Typical Applications

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KAD5512P

Contextual Info: Low Power 10-Bit, 250/210/170/125MSPS ADC D5510P Features The D5510P is a family of low power, high performance 10-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The

D5510

Abstract: BTD5510F3 transistor 406 specification BTD5510
Contextual Info: Spec. No. : C658F3 Issued Date : 2005.08.23 Revised Date :2006.11.29 Page No. : 1/3 CYStech Electronics Corp. NPN Epitaxial Planar Transistor D5510F3 Description The D5510F3 is a NPN Darlington transistor, designed for general purpose amplifier and low speed

Contextual Info: Pomona Model 5510 BNC To Banana Plug and Binding Post Adapter Kit MATERIALS: Model 1269: BNC Female To Double Stacking Banana Plug: Body: Brass, Nickel Plated, Dielectric: PTFE Center Contact: Beryllium Copper, Gold Plated, Banana Plug - Body: Brass, Nickel Plated, Spring: Beryllium Copper,

KAD5512P

Abstract: 120M 500MSPS KAD5510P-50 D5510
Contextual Info: Low Power 10-Bit, 250/210/170/125MSPS ADC D5510P Features The D5510P is a family of low power, high performance 10-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The

KAD5512P

Contextual Info: Low Power 10-Bit, 250/210/170/125MSPS ADC D5510P Features The D5510P is a family of low power, high performance 10-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The

D5510

Abstract: darlington transistor C 3300 BTD5510F3
Contextual Info: Spec. No. : C658F3 Issued Date : 2005.08.23 Revised Date : Page No. : 1/5 CYStech Electronics Corp. NPN Epitaxial Planar Transistor D5510F3 Description The D5510F3 is a NPN Darlington transistor, designed for general purpose amplifier and low speed switching application.

phc51

Abstract: A0317
Contextual Info: HYUNDAI H Y 5 1 V 1 6 1 6 0 B S e r ie s 1 M x 16-bit CMOS DRAM with 2ÜÄ5 DESCRIPTION T he H Y51V 16160B is th e new generation and fa st dynam ic RAM organized 1,048,576 x 16-bit. The HY51V16160B utilizes Hyundai’s CM OS silicon gate process technology as well as advanced circuit techniques

Contextual Info: NEC MOS INTEGRATED CIRCUIT juPD42S16805L, 4216805L 3.3 V OPERATION 16 M-BIT DYNAMIC RAM 2 M-WORD BY 8-BIT, HYPER PAGE MODE Description The /¿PD42S16805L, 4216805L are 2 097 152 words by 8 bits dynamic CMOS RAMs w ith optional hyper page mode. Hyper page mode is a kind o f the page mode and is useful fo r the read operation.