D5 Y0 Search Results

usb mp3player

Abstract: mp3player 74HC00 MAX232CSE 74HC138 K9FXX08UOB K746 LM1117 CS4331 DD10
Contextual Info: 1 2 1 Vin POWER D 3 VCC 3 Vout 4 R6 R7 R2 1K 2 1 5 R8 R9 VCC D1 LED C1 1000u 2 J2 GND J1 U1 LM1117 R1 1.5k POWER1 J3 R10 R12 R11 R13D0 D1 D2 D3 D4 D5 D6 D7 U2 D0 3 D1 4 D14 7 D15 8 D12 13 D13 14 D2 17 D3 18 D0 D1 D2 D3 D4 D5 D6 D7 1 11 5 4 3 2 1 Q0 Q1 Q2 Q3

ORP 112

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

2128-80LQ

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

65LVDS95Q

Abstract: DS90CR215 SN65LVDS95 SN65LVDS95DGGRQ1 SN65LVDS96 SN65LVDS95Q1
Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to DGG PACKAGE TOP VIEW 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

1032E

Abstract: ispLSI 1032E-100LJN 20037a 1032E-70ljn
Contextual Info: LeadFree Package Options Available! ispLSI 1032E In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates Output Routing Pool — 64 I/O Pins, Eight Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0

Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to DGG PACKAGE TOP VIEW 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

Contextual Info: SN65LVDS95ĆQ1 LVDS SERDES TRANSMITTER SGLS207A − OCTOBER 2003 − REVISED MAY 2008 DGG PACKAGE TOP VIEW D Qualified for Automotive Applications D 21:3 Data Channel Compression at up to 1.36 Gigabits per Second Throughput D4 VCC D5 D6 GND D7 D8 VCC D9

2128-80LT

Contextual Info: ® ispLSI and pLSI 2128 High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

lattice 1996

Contextual Info: ispLSI and pLSI 2128 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

1032E

Contextual Info: LeadFree Package Options Available! ispLSI 1032E In-System Programmable High Density PLD Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates Output Routing Pool — 64 I/O Pins, Eight Dedicated Inputs D7 D6 D5 D4 D3 D2 D1 D0

DS90C581

Abstract: SN75LVDS83
Contextual Info: SN75LVDS83 FLATLINK TRANSMITTER SLLS271 - M A R C H 1997 28:4 Data Channel Compression at up to 227.5 Million Bytes per Second Throughput DGG PACKAGE TOP VIEW • VCC [ 1 D5 [ 2 D6 [ 3 Suited for SVGA, XGA, or SXGA Display Data Transmission From Controller to

ASR16

Contextual Info: Freescale Semiconductor, Inc. Freescale Semiconductor, Inc. SECTION 6 INSTRUCTION SET AND EXECUTION Fetch F1 Decode Execute Instruction Cycle: 1 MOTOROLA F2 D1 F3 D2 E1 F3e D3 E2 F4 F5 F6 D3e D4 D5 E3 E3e E4 … … … 2 3 4 5 … 6 7 INSTRUCTION SET AND EXECUTION

Motorola DSP56k instruction set

Abstract: yx 801 DSP56K
Contextual Info: SECTION 6 INSTRUCTION SET INTRODUCTION Fetch F1 Decode Execute Instruction Cycle: 1 MOTOROLA F2 D1 F3 D2 E1 F3e D3 E2 F4 F5 F6 D3e D4 D5 E3 E3e E4 . . . . . . . . . 2 3 4 5 . . . 6 7 INSTRUCTION SET INTRODUCTION 6-1 SECTION CONTENTS SECTION 6.1 INSTRUCTION SET INTRODUCTION . 3

dsp56800 instruction opcode

Abstract: DSP56800 001C C00F CA79
Contextual Info: SECTION 6 INSTRUCTION SET INTRODUCTION Fetch Decode Execute Instruction Cycle: F1 F2 D1 F3 D2 E1 1 2 3 F3e F4 F5 D3 D3e D4 E2 E3 E3e 4 5 6 DSP56800 Family Manual F6 D5 E4 . . . 7 . 6-1 Instruction Set Introduction 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6-2 INTRODUCTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6-3

Contextual Info: Specifications ispLSI and pLSI 1032 ispLSI and pLSI 1032 ® High-Density Programmable Logic Functional Block Diagram IG N Output Routing Pool D7 D6 D5 D4 D3 D2 D1 D0 ES A1 A2 Logic A3 D Array A4 C5 D Q D Q GLB C4 C3 D Q A5 C2 A6 C1 EW Output Routing Pool

countdown timer code for 8051 with keypad

Abstract: intel 8051 opcode sheet DS2250 DS2250T DS5000 DS5000FP DS5000T DS5000TK PC15 interfacing of magnetic stripe with 8051
Contextual Info: USER’S GUIDE SECTION 19: INSTRUCTION SET DETAILS INSTRUCTION CODE ARIT ITHM METIC OP PERA ATION MNEMONIC HEX BYTE CYCLE EXPLANATION D7 D6 D5 D4 D3 D2 D1 D0 ADD A, Rn 1 1 n2 n1 n0 28–2F 1 1 A = (A) + (Rn) ADD A, direct a7 a6 1 a5 a4 a3 1 a2 a1 1 a0 25

Contextual Info: IDT29FCT520DTPY IL08 C-MOS MULTILEVEL PIPELINE REGISTERS —TOP VIEW— I0 IN 1 VDD 24 I1 IN 2 23 S0 OUT D0 IN 3 22 S1 OUT D1 IN 4 21 Y0 OUT D2 IN 5 20 Y1 OUT D3 IN 6 19 Y2 OUT D4 IN 7 18 Y3 OUT D5 IN 8 17 Y4 OUT D6 IN 9 16 Y5 OUT D7 IN 10 15 Y6 OUT CLK IN 11

1032-90LT

Contextual Info: ispLSI and pLSI 1032 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool IG N D7 D6 D5 D4 D3 D2 D1 D0 ES A2 Logic A3 Array D A4 A5 C5 D Q D Q GLB C4 C3 D Q EW Output Routing Pool C6 D Q C2 C1 A6 Global Routing Pool GRP C0 B0 B1 B2 B3 B4 B5 B6 B7

resistors 10k

Abstract: 74HC00 H5 RESISTORS 74HC157AD 56K2EVM hack x-tal DAB14
Contextual Info: D5 R15 J17 3 2 1 GREEN LED IRQA~ IRQB~ NMI 2 2 1 2 2 4 6 8 10 12 14 16 1 3 5 7 9 2 4 6 8 10 Port-B 1 3 5 7 9 11 13 15 74HC157AD B0 SELECT A0 B1 Y2 B2 Y1 Y0 A1 A2 B3 Y3 A3 O/E U16 DS~ PS~ BR~ BN~ HACK~ HEN~ HR/W~ H6 H4 H2 H0 12 9 7 4 1 2 CKOUT RESET~ BUS_CTRL

IA7 B

Abstract: UPD71055 74HC138 74HC04 NOT GATE datasheet SW-DIP-8 74F543 74HC04 DB10 IA10 ACT B5
Contextual Info: 8 7 6 5 4 3 1 2 D 34 33 32 31 30 29 28 27 U7 D0 D1 D2 D3 D4 D5 D6 D7 5 36 9 8 35 6 RD WR A0 A1 RESET CS CN1 GND1 A1 INT4* C1 GND1 A2 INT3* C2 GND1 A3 INT2* C3 GND1 A4 INT1* C4 GND1 A5 IORES* C5 GND1 A6 XACK* C6 GND1 A7 CLK C7 GND1 A8 RV1 C8 GND1 A9 (RV2) C9

SN75LVDS81

Abstract: SLLS258 7A1P
Contextual Info: SN75LVDS81 FLATLINK TRANSMITTER SLLS258 - N0VEMBER1996 - REVISED JANUARY 1997 D Û Û PACKAGE 2 8 : 4 D a t a C h a n n e l C o m p r e s s i o n a t u p to TOP VIEW 2 2 7 . 5 M i l l i on B y t e s p e r S e c o n d T h r o u g h p u t • V CC [ 1 D5 [ 2

Contextual Info: NJU6677 TERMINAL DESCRIPTION Chip Size 8.31 x 2.93mm Chip Center X=0um,Y=0um PAD No. Te rminal X = um Y= um PAD No. Te rminal X = um Y= um 1 D U M M Y0 -3884.0 -1305.0 51 C6 3 9 9 5 .0 -958.1 2 VDD -3179.2 -1305.0 52 C7 3 9 9 5 .0 -898.1 3 P /S -3014.1 -1305.0

74ls548

Abstract: 74LS549 SN74LS549 SN54LS548 SN54LS549 SN74LS548 SN54LS549JS
Contextual Info: 8-B it Two-Stage Pipelined Reg is te r/ Latch SN54/74LS548 SN54/74LS549 Feature/ Benefits • Two 8-bit high-speed registers/latches • Faster than other LS-TTL registers/latches the outputs Y7-Y0. This multiplexer is controlled by the OUTSEL line, and allows either the first o r second register/latch data to be