D399 Search Results

74ACT11867

Abstract: BOX655303
Contextual Info: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178 - D3990, DECEMBER 1991 - REVISED APRIL 1993 DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use Flow-Through Architecture Optimizes

SN74ACT1071

Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN74ACT1071

Abstract: d3994
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN74ACT1071

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT11086

Abstract: HC86
Contextual Info: 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS091 – D3990, NOVEMBER 1989 – REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

D3996

Contextual Info: TLC5502-5M 8-BIT ANALOG-TO-DIGITAL CONVERTER D3996, MA RCH 1992 J PACKAGE LinEPIC 1- xm CMOS Process (TOP VIEW 8-Bit Resolution Differential Linearity E rro r. . . ±0.2% Max Maximum Conversion R a te . . . 20 MHz Typ . . . 1 0 MHz Min D G TL G N D 1 [ 1 U

D3995

Contextual Info: TLE2144M, TLE2144AM EXCALIBUR LOW-NOISE HIGH-SPEED PRECISION QUAD OPERATIONAL AMPLIFIERS D3995, N O V E M B E R 1991 a v a ila b le fe a tu re s Low Noise: 10 Hz 1 kHz Low V|Q . . . 1.5 m V M ax at 25°C 15 nV/Vfiz 10.5 nV/VHz S in gle or Split S u p p ly . . .

SR57 battery

Abstract: D399 D-399 SR57 1125H
Contextual Info: SIZE D399 Silver Oxide Battery SR57 SPECIFICATIONS Minimum No Load Voltage: 1.55 V Minimum On Load Voltage: .84V on 22Ohms at 1000 Minimum Life 1125 H 34.8k Ohms Hr/Day 1.2 V Rated Capacity 50 mAh on 34.8kOhms to 1.2V Volume .18 cm3 Weight .78g Physical Size in mm

SN74ACT1073

Abstract: SCAS193
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SN74ACT1071

Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DR SN74ACT1071DRE4
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS091 – D3990, NOVEMBER 1989 – REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

SCAS193

Abstract: SN74ACT1073
Contextual Info: SN74ACT1073 16-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS193 – D3992, MARCH 1992 – REVISED APRIL 1993 • • • • • • • DW PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS091 – D3990, NOVEMBER 1989 – REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATE ą ą SCAS091 − D3990, NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

SN74ACT1071

Abstract: SN74ACT1071D SN74ACT1071DE4 SN74ACT1071DG4 SN74ACT1071DR SN74ACT1071DRE4
Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATE ą ą SCAS091 − D3990, NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: SN74ACT1071 10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION SCAS192 – D3994, MARCH 1992 – REVISED APRIL 1993 • • • • • • • D PACKAGE TOP VIEW Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot

control up/down 0-255

Abstract: 74ACT11867
Contextual Info: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178 – D3990, DECEMBER 1991 – REVISED APRIL 1993 • • • • • • • Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCAS091 – D3990, NOVEMBER 1989 – REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11086

Contextual Info: 74ACT11086 QUADRUPLE 2ĆINPUT EXCLUSIVEĆOR GATE ą ą SCAS091 − D3990, NOVEMBER 1989 − REVISED APRIL 1993 • • • • • • D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations