D341 Search Results

VLR175LF

Abstract: BU-75K
Contextual Info: PolySwitch PTC Devices 308 Constitution Drive Menlo Park, CA 94025-1164 Phone: 800-227-4856 www.circuitprotection.com PRODUCT : VLR175LF DOCUMENT: SCD 25533 PCN: D34121 REV LETTER: E REV DATE: JUNE 25, 2007 PAGE NO.: 1 OF 1 Overcurrent Protection Device

SN100KT5574

Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS009 – D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

54AC11379

Abstract: 54ACT11379 74AC11379 74ACT11379 D3414
Contextual Info: 54AC11379, 74AC11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0143— D3414, MAHCH 1990 Clock Enable Latched to Avoid False Clocking 54AC11379 . . . J PACKAGE 74AC11379 . . . DW OR N PACKAGE <TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

TI0148

Abstract: D3419 74ACT11379 54ACT11379 54AC11379 TI0148-D3419
Contextual Info: 54ACT11379, 74ACT11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0148— D3419, M ARCH 19 Inputs Are TTL-Voltage Compatible 54ACT11379 . . J PACKAGE 74ACT11379 . . . DW OR N PACKAGE • Clock Enable Latched to Avoid False Clocking TOP VIEW • Applications Include: Buffer/Storage

d3413

Abstract: BCT8244 54BCT8244 SCBS042-TI0037-D3413 74BCT8244 74BCT244 SN74BCT8244 Texas Instruments bct8244
Contextual Info: SN54BCT8244, SN74BCT8244 SCAN TEST DEVICES WITH OCTAL BUFFERS SCBS042— TI0037— D3413, FEBRUARY 1990 Members of Texas Instruments SCOPE Family of Testability Products SN54BCT8244 . . . JT PACKAGE SN74BCT6244 . . . DW OR NT PACKAGE TOP VIEW Octal Test Integrated Circuits

54AC11244

Abstract: ac11244 74AC 74AC11244 162A3
Contextual Info: 54AC11244, 74AC11244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0074— D3411, MAY 1987— REVISED MARCH 1990 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers S 4A C 11244 . . . J T P ACKA G E 7 4A C 11 2 44 . . . D W O R N T P A C K A G E

Contextual Info: 54ACT11240, 74ACT11240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0072— D3410, M AY 1987— R E V IS E D M A R C H 1990 54ACT11240 . . . JT P A C K A G E 74ACT11240 . DW O R NT P A C K A G E • Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PC B

Contextual Info: 54AC11379, 74AC11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0143— D3414, MARCH 1990 54AC11379 . J PACKAGE 74AC1137S . DWORNPACKAGE TOP VIEW 1Q[ 1 20 ]1Q 2Q[ 2 19 ] CLKEN 2Q[ 3 18 ]1D gnd[ 4 17 ] 2D gnd[ 5 16 ] Vcc gnd[ 6 15 IVCC gnd[ 7 14] 3D 3Q[ 8 13) 4D

Contextual Info: SN100KT5574 OCTAL ECLĆTOĆTTL TRANSLATOR WITH DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS AND 3ĆSTATE OUTPUTS SDZS009 − D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

SN100KT5574

Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS _ D3418. JANUARY 1990-flEVISED OCTOBER 1990 DW OR NT PACKAGE TO P V IE W * 100K Compatible * ECL Clock and TTL Control Inputs

54AC11379

Abstract: 54ACT11379 74AC11379 74ACT11379 d3414
Contextual Info: 54AC11379, 74AC11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0143— D3414, MAHCH 1990 Clock Enable Latched to Avoid False Clocking 54AC11379 . . . J PACKAGE 74AC11379 . . . DW OR N PACKAGE <TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

SN100KT5574

Contextual Info: SN100KT5574 OCTAL ECLĆTOĆTTL TRANSLATOR WITH DĆTYPE EDGEĆTRIGGERED FLIPĆFLOPS AND 3ĆSTATE OUTPUTS SDZS009 − D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

cq037

Abstract: SN74ACT2155
Contextual Info: SN74ACT2156 16K x 4 BURST CACHE ADDRE SS COMPARATOR/DATA RAM D3412, APRIL 1990-RÊVISED JUNE 1990 • Cache Data RAM with Parity and Internal Burst Counter • Dirty Bit Storage Capability for Use in Copy-Back Caches • Separate I/O Supports Copy-Back TOP VIEW

Contextual Info: 54ACT11379, 74ACT11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0148— D3419, MARCH 1990 Inputs Are TTL-Voltage Compatible 54ACT11379 . . . J PACKAGE 74ACT11379 . . . DW OR N PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW Applications Include: Butfer/Storage

Contextual Info: PolySwitch PTC Devices PRODUCT : VLR175LF DOCUMENT: SCD25533 PCN: D34121 REV LETTER: F REV DATE: MAY 11, 2011 PAGE NO.: 1 OF 1 Overcurrent Protection Device 308 Constitution Drive Menlo Park, CA 94025-1164 Phone: 800-227-4856 www.circuitprotection.com Specification Status: Released

74ACT11240

Abstract: 54ACT11240
Contextual Info: 54ACT11240, 74ACT11240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS TI0072— D3410, M AY 1987— R EVISED MARCH 1990 54AC T11240 . . . J T PAC KAG E 74AC T11240 . . . D W OR NT PAC KAG E • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB

74ACT11810

Abstract: 54ACT11810
Contextual Info: 54ACT11810, 74ACT11810 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES TI0172— D3416, MARCH 1990 S4ACT11810 . . . J PACKAGE 74ACT11810 . . D OH N PACKAGE Inputs are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout TOP VIEW 1A[ 1Y[ 2Y[ GND[

D172D

Abstract: D3419 ttwm
Contextual Info: 54ACT 11379, 74ACT11379 QUAD D-TYPE FLIP-FLOPS WITH CLOCK ENABLE TI0148— D3419, MARCH 1990 54ACT11379 . . . J PACKAGE 74ACT11379 . . . DW OR N PACKAGE Inputs Are TTL-Voltage Compatible Clock Enable Latched to Avoid False Clocking TOP VIEW Applications Include: Buffer/Storage

SN100KT5574

Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS009 – D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

SN100KT5574

Abstract: SN100KT5574DW SN100KT5574NT
Contextual Info: SN100KT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS SDZS009 – D3418, JANUARY 1990 • • • • • DW OR NT PACKAGE TOP VIEW 100K Compatible ECL Clock and TTL Control Inputs Flow-Through Architecture Optimizes PCB

Contextual Info: TEXAS XNSTR LOGIC 31E D m 6 ^ 1 7 2 3 0063741 3 M T I I 3 54ACT11240, 74ACT1124Q OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T ' 5 2 ' 0 7 - 0 TI0072— D3410, M AY 1987— REVISED MARCH 1990 Inputs are TTL-Voltage Compatible 54AC T11240 . . . J T PACKAGE

P3417

Abstract: D3417 SN10KHT5574
Contextual Info: SN10KHT5574 OCTAL ECL-TO-TTL TRANSLATOR WITH D-TYPE EDGE-TRIGGERED FLIP-FLOPS AND 3-STATE OUTPUTS _ D3417, JANUARY 1990-REVISED OCTOBER 1990 □W OR NT PACKAGE TOP VIEW 10KH Compatible ECL Clock and TTL Control Inputs

ptc 240 L012

Abstract: 240 L012
Contextual Info: Tyco / Electronics PolySwitch PTC Devices Raychem Circuit Protection 308 Constitution Drive Menlo Park, CA 94025-1164 Phone: 800-227-4856 Fax: 800-227-4866 PRODUCT: LVR012S-1 DOCUMENT: SCD 25287 PCN: D34159 REV LETTER: F REV DATE: NOVEMBER 24, 2003 PAGE NO.: 1 OF 2

Contextual Info: 54ACT11810, 74ACT11810 QUADRUPLE 2-INPUT EXCLUSIVE-NOR GATES T 10172— D3416, MARCH 1990 • Inputs are TTL-Voltage Compatible 54ACT11810 . . . J PACKAGE 74ACT11810 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout TOP VIEW • Center-Pin Vcc and GND Configurations to