D320 Search Results

d3207

Abstract: 54f38
Contextual Info: SN54F38, SN74F38 QUADRUPLE 2-INPUT POSITIVE-NAND BUFFERS WITH OPEN-COLLECTOR OUTPUTS D3207, JANUARY 1989 SN 54F38 . . . J PACKAGE SN74F38 . D OR N PACKAGE Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

PHL 99

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER _ SCAS055A - D3201, APRIL 1989 - REVISED APRIL 1993 D OR N PACKAGE TOP VIEW * Generates Either Odd or Even Parity for Nine Data Unes * Cascadable for n-BKs Parity B[ A[ £ ODD [ GND [ 2 EVEN [ NC [ ll * Flow-Through Architecture to Optimize

MC3486

Abstract: SN75ALS194 SN75ALS199
Contextual Info: SN75ALS199 QUAD DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS SLLS0468 - D3204. JANUARY 1 9 8 9 - REVISED MARCH1993 Meets CCITT Recommendations V.10, V.11, X.26, and X.27 -7 V to 7 V Common-Mode Input Voltage Range With 300-mV Sensitivity 3-State TTL-Compatible Outputs

Contextual Info: 74AC11280 9-BIT PARITY GENERATOR/CHECKER SCAS055A – D3201, APRIL 1989 – REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Parity Flow-Through Architecture to Optimize

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: bl D3201 0Dlö7bS 405 25LC320 M ic r o c h ip 32K 2.5V SPI Bus Serial EEPROM r TM FEATURES PACKAGE TYPES • SPI modes 0,0 and 1,1 • 3.0 MHz Clock Rate • Single supply with Programming Operation down to 2.5V • Low Power CMOS Technology - Max Write Current: 5.0 mA

TO-251 Outline

Contextual Info: STU/D320S S a mHop Microelectronics C orp. Ver 1.0 N-Channel Logic Level Enhancement Mode Field Effect Transistor FEATURES PRODUCT SUMMARY V DSS Super high dense cell design for low R DS ON . R DS(ON) (m Ω) Max ID Rugged and reliable. 20 @ VGS=10V TO-252 and TO-251 Package.

Power supply ATX 350W p4

Abstract: ATX 350W p4 Power supply ATX 400W p4 MPI-810H 12v dc to atx pc Power Supply GADIWA-3120 12v dc to atx p4 atx 400w GADIWA-3161 Power supply ATX 300W p4
Contextual Info: PSU Reference Table ORION-A2501 ORION-D5501P ORION-D3202P ORION-D4602P ORION-B3502 MPM-842P MPI-815H MPI-810H MPI-806H TYPE MODEL FORM FACTOR DIMENSION POWER RANGE PAGE Single GADIWA-P0901 DC/DC 60 x 45 x 15 mm 120W / ATX Output 135 Wide-Range GADIWA-R9271

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR ą ą SCAS086 − D3200, OCTOBER 1989 − REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: SERIES: VF-D320-DXXA-CFS date 08/28/2012 page 1 of 5 DESCRIPTION: AC-DC POWER SUPPLY FEATURES • • • • • • • • • • up to 320 W continuous power metal top cover and side fan passive power correction dual outputs power good signal remote on/off control

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

74AC11280

Abstract: L-13
Contextual Info: 74AC11280 9ĆBIT PARITY GENERATOR/CHECKER ą ą SCAS055A − D3201, APRIL 1989 − REVISED APRIL 1993 • • • • • • • D OR N PACKAGE TOP VIEW Generates Either Odd or Even Parity for Nine Data Lines Cascadable for n-Bits Parity Flow-Through Architecture to Optimize

AXICOM Relay Fx2 d3204

Abstract: D3204 axicom fx2 d3204
Contextual Info: D3204 Product Details C om m u n ication s / S ignal PC Board Re lays Converted to EU RoHS/ELV Compliant Statement of Compliance Previous 1 . 6 [7] 8 9 10 . 20 Next Quick Links Check Pricing & Availability Search for Tooling Product Feature Selector

AXICOM Relay Fx2 D3202

Abstract: FX2 D3202 d3202
Contextual Info: D3202 Product Details C om m u n ication s / S ignal PC Board Re lays Converted to EU RoHS/ELV Compliant Statement of Compliance Previous 1 . [6] 7 8 9 10 . 20 Next Quick Links Check Pricing & Availability Search for Tooling Product Feature Selector

LT1054m

Abstract: LT 752 d3202
Contextual Info: LT1054 SWITCHED-CAPACITOR VOLTAGE CONVERTER WITH REGULATOR D3202, JANUARY 1969 • O u tp u t C urrent . . . 1 0 0 m A • Lo w Loss . . . 1.1 V a t 1 0 0 m A JG AND P PACKAGE {TOP VIEW TOT Jvcc 7 • O perating Range . . . 3 .5 V to 15 V • R eference and Error A m p lifie r fo r Regulation

d3208

Abstract: SN54F40 SN74F40
Contextual Info: SN54F40, SN74F40 DUAL 4-INPUT POSITIVE-NAND BUFFERS D3208, JANUARY 1989 TOP VIEW 1B C 2 NC C 3 IC C A 1D C 5 1Y c 6 GND C 7 description These devices contain tw o independent 4-input NAND buffer gates. They perform the Boolean functions Y = A *B » C *D o rY = A + B + C + D in

74ACT11181

Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 - D3200, OCTOBER 1989 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations Minimize High-Speed Switching Noise

AM26LS32A

Abstract: RS-422-A SN75ALS192 SN75ALS197 SN75ALSI97 d3203
Contextual Info: ^ SN75ALS197 QUAD DIFFERENTIAL LINE RECEIVER WITH 3-STATE OUTPUTS S U -S 045A - D3203, JA N U A R Y 1989 - REVISED MARCH 1993 Meets CCITT Recommendations V.10, V.11 X.26, and X.27 ’ Designed for Multipoint Bus Transmission on Long Bus Lines in Noisy Environments

SN74F40

Contextual Info: SN54F40, SN74F40 DUAL 4-INPUT POSITIVE-NAND BUFFERS D3208, J A N U A R Y 1989 SN 54F40 . . . J PACKAG E S N 7 4 F 4 0 . . D OR N P A C K A G E Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil

74ACT11181

Contextual Info: I 31E D TEXAS INSTR LOGIC • ^(31723 DQflflbS? fi ■ T I I 3 54ACT11181, 74ACT11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T-MQ-I/-00 TI0183— D3200, OCTO BER 1989—REVISED M AR C H 1990- 54ACT11fS1 . . . JT PACKAGE 74A C T 11181 . . . DW O R NT PACKAGE

DDR200

Abstract: DDR266A
Contextual Info: D a t a S h e e t , R e v . 1 . 0 3 , J a n . 2 00 4 HYS[64/72]D16000GU-[7/8]-A HYS[64/72]D32020GU-[7/8]-A Unbuff ered DDR SDRAM- Modul es DDR SDRAM M e m or y P r o du c t s N e v e r s t o p t h i n k i n g . Edition 2004-01 Published by Infineon Technologies AG,

act118

Abstract: 74ACT11181
Contextual Info: 74ACT11181 ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR SCAS086 – D3200, OCTOBER 1989 – REVISED APRIL 1993 • • • • • • • • DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible New Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations