D29S7 Search Results

Contextual Info: 54ACT11109,74ACT11109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ D29S7, FEBRUARY 1987 - REVISED APRIL 1993 54ACT11109. . . J PACKAGE 74ACT11109 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible

74AC11520

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987 - REVISED APRIL 1993 54AC11520 . . . J PACKAGE 74AC11S20. . . DW OR N PACKAGE TOP VIEW Compares TVvo 8-Bit Words Flow-Through Architecture Optimizes PCB Layout Center-PIn Vcc and GND Configurations

Contextual Info: 54ACT11534,74ACT11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS SCASQ38A- D2957, JULY 1987 - REVISED APRIL 1883_ logic diagram positive logic logic symbolt 24 55 rs 13 >C 1 CLK n 1D r i 2 2D _ _ 1Q 1Q 1D •V 20 3 4

Contextual Info: 54AC11021,74AC11021 DUAL 4-INPUT POSITIVE-AND GATES _ D 2957, JULY 1987 - R EVISED APRIL 1993 * Flow-Through Architecture Optimizes PCB Layout 54AC11021 . . . J PACKAGE 74AC11021 . . . D OR N PACKAGE TOP VIEW * Center-Pin Vcc and GND Configurations

74AC11646

Abstract: D2957
Contextual Info: 74AC11646 OCTAL BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS _ P2957, JULY 1987 - REVISED APRIL 1993 * Independent Registers for A and B Buses * Multiplexed Real-Time and Stored Data * Flow-Through Architecture Optimizes PCB Layout

Contextual Info: t 31E O' TEXAS INSTR LOGIC 3 ^ 1 7 2 3 QQflfl^Qb 3 BITII3 54ACT11533, 74ACT11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS T 'M - C e ’ O 1 ~ 11 TI0086— D2957, JU LY 1987— REVISED MARCH 1990 S4ACT11533 . . . JT PACKAGE 74ACT11533 . . . DW OR NT PACKAGE

Contextual Info: 54ACT11021, 74ACT11021 DUAL 4-INPUT POSITIVE-AND GATES SCAS012B - P2957, JULY 1978 - REVISED APRIL 1993 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GND Configurations

qk 69 snd

Abstract: D2987
Contextual Info: 74AC11158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER D2957, JULY 1989 - REVISED A P R IL 1993 DW OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin V c c and GND Pin Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES SCAS008B-D2957, JULY 1987-REVISEDAPRIL1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Oenter-PIn V^c and GND Configurations to Minimize High-Speed Switching Noise

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS/LINE DRIVERS WITH 3-STATE OUTPUTS SCAS011B - D2957, JULY 1987 - REVISED APRIL 1993 * 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers * Inputs Are TTL-Voltage Compatible * Flow-Through Architecture Optimizes

Contextual Info: 54AC11534,74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D2957, JULY 1987-REVISED APRIL 1993 * * * * * * * * * Eight D-Type Flip-Flops In a Single Package 3-State Bus Driving Inverting Outputs Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible

TJ53L

Abstract: 54AC11646 74AC11646 D2957
Contextual Info: TEXAS I NSTR LOGIC 3i E » m 6^1723 aoaflisi 2 miii3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS \ — ' V— ) C > TI0097— D2957i JULY 1987— REVISED MARCH 1990 54AC11646 JT PACKAGE 74AC11646 . . . DW OR NW PACKAGE

Contextual Info: 74AC11157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS183 - D2957, JULY 1989 - REVISED APRIL 1993 DW OR N PACKAGE {TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin Vcc and GND Pin Configurations Minimize High-Speed Switching Noise

Contextual Info: 54ACT11533,74ACT11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS SCAS017A- D2957, JULY 1987 - REVISED APRIL 1993 Eight Latches In a Single Package 3-State Bus-Driving Inverting Outputs Full Parallel Access for Loading Buffered Control Inputs Inputs Are TTL-Voltage Compatible

16 line to 4 multiplexer IC

Contextual Info: 74AC11157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCAS183 - D2957, JULY 1989 - REVISED APRIL 1993 Flow-Through Architecture Optimizes PC B Layout DW O R N PACKAGE TOP VIEW Center-PIn V c c and GND Pin Configurations Minimize High-Speed Switching Noise

Contextual Info: 54AC11011,74AC11011 TRIPLE 3-INPUT POSITIVE-AND GATES D2957, JULY 1987-R E V IS E D APRIL 1993 Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GND Configuration Minimizes High-Speed Switching Noise EPIC'“ Enhanced-Performance Implanted

54ACT11245

Contextual Info: 54ACT11245, 74ACT11245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS031B - D2957, JULY 1987 - RE V IS E D A P R IL 1993 54ACT11245. . . JT PACKAGE 74ACT11245. . . DB, DW, NT, OR PW PACKAGE * 3-State Outputs Drive Bus Lines Directly f * Inputs Are TTL-Voltage Compatible

Contextual Info: 54ACT11034, 74ACT11034 HEX NONINVERTERS SC AS035A - D2957, FEBRUAHV 1988 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible 54ACT11034 . . . J PACKAGE 74ACT11034 . . . DW OR N PACKAGE Flow-Through Architecture Optimizes PCB Layout TOP VIEW Center-FIn V c c and GND Configurations

Contextual Info: 54AC11011, 74AC11011 TRIPLE 3-INPUT POSITIVE-AND GATES D2957, JULY 1987 - RE V IS E D A P R IL 1993 54AC11011 . . J PACKAGE 74AC11011 . . . D OR N PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout Center-Pin V c c and GND Configuration Minimizes High-Speed Switching Noise

Contextual Info: 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS018A —D2957, JULY 1 9 8 7 -R E V IS E D A P R IL 1 9 9 3 54ACT11010. . . J PACKAGE 74ACT11010. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible * Flow-Through Architecture to Optimize PCB Layout

74AC11533

Abstract: D204D
Contextual Info: 54AC11533, 74AC11533 OCTAL D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS D2957, JULY 1987 - RE V IS E D APRIL 1993 8-Latches in a Single Package 54AC11533 . . . JT PACKAGE 74AC11533. . . DW OR NT PACKAGE 3-State Bus-Driving Inverting Outputs TOP VIEW Full Parallel Access for Loading

Contextual Info: 54AC11520,74AC11520 8-BIT IDENTITY COMPARATORS D2957, JULY 1987-R EVISED APRIL1993 I | * Compares Two 8-Bit Words • Flow-Through Architecture Optimizes PCB Layout 54AC11520. . . J PACKAGE 74AC11520. . . DW OR N PACKAGE TOP VIEW • Center-Pin V^c and GND Configurations

AC11534

Contextual Info: 54AC11534,74AC11534 OCTAL D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D2957, JULY 1987 - REVISED APRIL 1933 Eight D-Type Flip-Flops in a Single Package 54AC11534 . . . JT PACKAGE 74AC11534 . . . DW OR NT PACKAGE TOP VIEW 3-State Bus Driving Inverting Outputs

54ACT11008

Contextual Info: 54ACT11008,74ACT11008 QUADRUPLE 2-INPUT POSITIVE-AND GATES SCASQ138 - D2957. AUGUST 1987 - REVISED APRIL 1983 Inputs Are TTL-Vottage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn Vcc and GND Configurations Minimize High-Speed Switching Noise