D24D31 Search Results

HIP-66

Contextual Info: FLASH AS8FLC1M32 FIGURE 1: PIN ASSIGNMENT Top View Hermetic, Multi-Chip Module (MCM) 32Mb, 1M x 32, 3.0Volt Boot Block FLASH Array Available via Applicable Specifications: • MIL-PRF-38534, Class H FEATURES • • • • • • • • • • • •

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

Contextual Info: in te i 386 DX MICROPROCESSOR HIGH PERFORMANCE 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

Contextual Info: ARM-based Embedded MPU SAM9G35 DATASHEET Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926EJ-S embedded MPUs that support high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation,

PX3-2

Abstract: AT32UC3A0256 128f 385P AT32UC3A0512
Contextual Info: Features • High Performance, Low Power 32-Bit Atmel AVR® Microcontroller • • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instruction Set – Read-Modify-Write Instructions and Atomic Bit Manipulation

ATMEL 234

Abstract: how to derive sim 900 ARM926EJ-S AT91SAM ISO7816
Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16-Kbyte Data Cache, 16-Kbyte Instruction Cache, Write Buffer

lfxp2-40e

Abstract: LVCMOS25 LD48 LFXP2-17E-5FTN256C HB1004 ispLEVER project Navigator route place LFXP2-5E-5QN IPUG35 LFXP2-8E
Contextual Info: LatticeXP2 Family Handbook HB1004 Version 02.9, May 2011 LatticeXP2 Family Handbook Table of Contents May 2011 Section I. LatticeXP2 Family Data Sheet Introduction Features . 1-1

RF 351

Abstract: multi format memory card reader KPS seven segment display SMC62 AC97 AT32AP7001 AVR32 Pin connection of bk 1085 HS 153 SP "BANDGAP REFERENCE" cross
Contextual Info: Features • High Performance, Low Power AVR 32 32-Bit Microcontroller • • • • • • • • • • • • • • • • • – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems

STP3010

Abstract: SUN HOLD ras 0910 ras 0910 STP3010PGA display duplo 27C256 MARK 4C7 BT467
Contextual Info: STP3010 July 1997 TGX DATA SHEET TurboGX Graphics Accelerator DESCRIPTION The STP3010 employs over 128,000 gates and implements an extended superset of previous GX architectures. This chip provides an integral SBus interface, VRAM video random-access memory controller, a high-performance math engine, plus a high-performance rendering (or drawing) engine. A complete graphics

T45 12H

Abstract: memory decoding 80386dx 16 bit sl90 LIM EMS 4.0 N804CS
Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • • • • • • Synchronous or Asynchronous System Control Operation.

TM248GBK32

Abstract: TM124BBK32 TM248CBK32
Contextual Info: TM124BBK32H, TM124BBK3211048576 BY 32-BIT TM248CBK32H, TM248CBK3212097152 BY 32-BIT DYNAMIC RAM MODULES S M M S 679-M A R C H 1997 • • Single 5-V Power Supply ±10% Tolerance • 72-Pin Single In-Line Memory Module (SIMM) fo r Use With Socket • Presence Detect

A 434 RF Receiver TRANSMITTER PAIR

Abstract: AT45DB161B pam 8304 bcfk AUTOMATIC ROOM LIGHT CONTROLLER using ldr abstract AT91RM9200 SDRAM XC-01
Contextual Info: Features • Incorporates the ARM920T ARM Thumb® Processor • • • • • • • • • • • • • • • • – 200 MIPS at 180 MHz, Memory Management Unit – 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer – In-circuit Emulator including Debug Communication Channel

485TurboCache

Abstract: 82485MA-33 2716 intel 82485MB
Contextual Info: INTEL CORP UP/PRPHLS SbE ]> 4öHbl?S Ollllb^ 31fi in y 485TURBOCACHE MODULE 'TMb-2.3-14 Intel486 MICROPROCESSOR CACHE UPGRADE 82485MA (64k Module) 82485MB (128k Module) High Integration — Seven Square Inch Area — Includes Tag, Data, Parity, and Controller

Contextual Info: FLASH AUSTIN SEMICONDUCTOR, INC. AS8FLC1M32 Austin Semiconductor, Inc. FIGURE 1: PIN ASSIGNMENT Top View • • • • • • • OPTION Access Speed 70ns 90ns 100ns 120ns MARKING -70 -90 -100 -120 61 62 63 64 65 66 67 68 01 02 03 04 05 06 76 15 55 16

Contextual Info: Features • Core • • • • • • – ARM926EJ-S ARM Thumb® Processor running at up to 400 MHz @ 1.0V +/- 10% – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,

ARM7TDMI System Peripherals

Abstract: program key lock ic 4013 154WA SAM7SE512 at91sam7sexx
Contextual Info: Features • Incorporates the ARM7TDMI ARM® Thumb® Processor • • • • • • • • • • • – High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE In-circuit Emulation, Debug Communication Channel Support

ATMEL 910

Abstract: atmel910 SMC911 hsb 772 p interface bluetooth with AVR ptz decoder AC97 AT32AP7000 AVR32 rf mems switch
Contextual Info: Features • High Performance, Low Power AVR 32 32-Bit Microcontroller • • • • • • • • • • • • • • • • • • • – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems

EM4450

Abstract: EM4550 marking code D23
Contextual Info: EM MICROELECTRONIC - MARIN SA EM4450 EM4550 1 KBit Read/Write Contactless Identification Device Description Features The EM4450/4550 is a CMOS integrated circuit intended for use in electronic Read/Write RF Transponders. The difference between EM4450 and EM4550 is that EM4550

intel i386 ex circuit diagram

Abstract: intel 80368 Instruction set Architecture i386 ex board M82384 i386 dx ICE-386 271052 271062 i386 SL M8088
Contextual Info: SñE J> • intei 462bl75 D I S H E D 17T ¡ITL1 INTEL CORP ÜP/PRPHLS ' T ' L t cv - n - y t - f MILITARY ¡386 HIGH PERFORMANCE 32-BIT MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Flexible 32-Bit Microprocessor — 8, 16, 32-Bit Data Types — 8 General Purpose 32-Bit Registers

Contextual Info: Features • Core • • • • • • • – ARM926EJ-S ARM Thumb® Processor running at up to 400 MHz @ 1.0V +/- 10% – 16 Kbytes Data Cache, 16 Kbytes Instruction Cache, Memory Management Unit Memories – One 64-Kbyte internal ROM embedding bootstrap routine: Boot on NAND Flash,

Contextual Info: .,f,i . . ,.:.:,;ri, ,.:. , ,.:,+:. . . . .4., ? >.,“ .s, ,. .,. ., c .,. , ,. $ ., ,. . ., s ., .,., ! .,.,.,. : .”,>. . . . . . . . . ,., , . . . . . . . . ., ., , .,., , . . . . Order this document Freescale Semiconductor, Inc.

6242E

Abstract: 4583 dual schmitt trigger 6242b la 4508 ic pin diagram R1100D121C AT91Bootstrap CS 5609 ARM926EJ-S ISO7816 5609 dec
Contextual Info: Features • Incorporates the ARM926EJ-S ARM Thumb® Processor • • • • • • • • • • – DSP Instruction Extensions – ARM Jazelle® Technology for Java® Acceleration – 16 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer