D16D3 Search Results

atmel 324

Abstract: ARM926EJ-S AT91SAM ISO7816 SAM9G45 AT91SAM9G45B-CU UHP4 ddr2 16bit NAND Flash controller ecc DFSDM
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDRAM/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDRAM/LPSDR, Static

Acc 2089

Abstract: ACC MICRO 2089 acc micro 2168 acc micro 2048 ACC MICRO 2086 ACC Microelectronics Corporation ACC Microelectronics ACC MICRO 2178 acc micro 2016 acc micro 2066
Contextual Info: 2016 ACC MICRO 2016 BUFFER AND MUX LOGIC DATA BOOK MARCH 1997 Revision 2.0 ACC Microelectronics Corporation, 2500 Augustine Drive, Santa Clara, CA 95054 Phone: 408 980-0622 Fax: (408) 980-0626 TM ACC Micro 2016 ACC Microelectronics Corporation 2500 Augustine Drive,

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS07-16309-2E 32-Bit Microcontroller CMOS FR65E Series MB91307A • DESCRIPTION The FUJITSU FR family of single-chip microcontrollers using a 32-bit high-performance RISC CPU, with a variety of built-in I/O resources and bus control mechanisms for built-in control applications requiring high-capability, highspeed CPU processing. External bus access is assumed in order to support the expanded address space accessible by the 32-bit CPU, and a 1 KB cache memory plus large 128 KB RAM are provided for high-speed

KL SN 102 94v

Abstract: wire T568 SCV64 The VMEbus Handbook, Fourth Ed VMEbus interface handbook Q002 ih 584 el designer manual kds 1555 SAA 1260 Ka 2535
Contextual Info: O p e n b u s In t e r fa c e C o m p o n e n t s SCV64 User Manual Issue 1 * / • bSflfllDl Q[ D24A0 134 ■ This Material Copyrighted By Its Respective Manufacturer T h e in fo rm a tio n in th is d o c u m e n t is su b je c t to c h a n g e w ith o u t n o tic e an d sh o u ld n o t be c o n stru ed as a

DFSDM

Abstract: SAM9M10 K 2141 AC97 ARM926EJ-S AT91SAM ISO7816 NBC 3111 hc 541 rfid reader id-20
Contextual Info: Features • 400 MHz ARM926EJ-S ARM Thumb® Processor – 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories • • • • – DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR – External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static

MMCX decoupling TOOL

Abstract: 6691 USB connector
Contextual Info: AM3517/05 ARM Microprocessor www.ti.com SPRS550 – OCTOBER 2009 1 AM3517/05 ARM Microprocessor 1.1 Features AM3517/05 ARM Microprocessor: – Software Compatible with OMAPTM 3 Processors* – MPU Subsystem • 500-MHz ARM Cortex-A8 Core • NEON SIMD Coprocessor and Vector

CD 2399 GP

Abstract: 80387 DX Users Manual Programmers Reference
Contextual Info: PRByBJOODOÂIfflr in t e i Intel486 DX MICROPROCESSOR 168-Pin Grid Array Package High Performance Design — RISC Integer Core with Frequent Instructions Executing in One Clock — 25 MHz, 33 MHz, and 50 MHz Clock — 80, 106, 160 Mbyte/sec Burst Bus — CHMOS IV and CHMOS V Process

Contextual Info: in te i 386 DX MICROPROCESSOR HIGH PERFORMANCE 32-BIT CHMOS MICROPROCESSOR WITH INTEGRATED MEMORY MANAGEMENT Optimized for System Performance — Pipelined Instruction Execution — On-Chip Address Translation Caches — 20, 25 and 33 MHz Clock — 40, 50 and 66 Megabytes/Sec Bus

hall marking code A04

Abstract: INTELDX4 write-through YSS 928
Contextual Info: INTEL486 PROCESSOR FAMILY • lntelDX4TM P ro c e s s o r — Up to 100-MHz Operation -Speed-M ultiplying Technology — 32-Bit Architecture — 16K-Byte On-Chip Cache — Integrated Floating-Point Unit — 3.3V Core Operation with 5V Tolerant I/O Buffers

Contextual Info: AT91SAM ARM-based Embedded MPU SAM9X35 SUMMARY DATASHEET Description The SAM9X35 is a highly-integrated 400 MHz ARM926EJ-S embedded MPU, featuring an extensive peripheral set and high bandwidth architecture for industrial applications that require refined user interfaces and high-speed communication.

Contextual Info: ARM-based Embedded MPU SAM9G35 DATASHEET Description The SAM9G35 is a member of the Atmel series of 400 MHz ARM926EJ-S embedded MPUs that support high bandwidth communication and advanced user interfaces and are optimized for industrial applications such as building automation,

Contextual Info: AT91SAM ARM-based Embedded MPU SAM9263 Description The AT91SAM9263 32-bit microcontroller, based on the ARM926EJ-S processor, is architectured on a 9-layer matrix, allowing a maximum internal bandwidth of nine 32-bit buses. It also features two independent external memory buses, EBI0 and EBI1, capable of interfacing with a wide range of memory devices and an IDE hard disk. Two external buses prevent

Contextual Info: ARM-based Embedded MPU SAM9N12 SAM9CN11 SAM9CN12 SUMMARY DATASHEET Description Based on the ARM926EJ-S processor, the Atmel SAM9N12/CN11/CN12 devices offer the frequently-requested combination of user interface functionality and high data rate connectivity, with LCD Controller, resistive touch-screen, multiple UARTs, SPI,

AT91SAM9260B-CU

Abstract: AT91SAM9260B-QU application note SAM9260
Contextual Info: Features • 180 MHz ARM926EJ-S ARM Thumb® Processor – 8 KBytes Data Cache, 8 KBytes Instruction Cache, MMU • Memories • • • • – 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC

RF 351

Abstract: multi format memory card reader KPS seven segment display SMC62 AC97 AT32AP7001 AVR32 Pin connection of bk 1085 HS 153 SP "BANDGAP REFERENCE" cross
Contextual Info: Features • High Performance, Low Power AVR 32 32-Bit Microcontroller • • • • • • • • • • • • • • • • • – 210 DMIPS throughput at 150 MHz – 16 KB instruction cache and 16 KB data caches – Memory Management Unit enabling use of operating systems

Contextual Info: UG7128D65Q4LQ Data sheets can be downloaded at www.unigen.com 1G Bytes 128M x 64 bits SYNCHRONOUS DRAM MODULE 184 Pin DDR SDRAM Register & PLL DIMM based on 16 pcs 128M x 4 Stacked DDR SDRAM 8K Refresh FEATURES PIN ASSIGNMENT (Front View) • • • •

Contextual Info: UG7128D6584KV Data sheets can be downloaded at www.unigen.com 1G Bytes 128M x 64 bits SYNCHRONOUS DRAM MODULE 184 Pin DDR SDRAM Register & PLL DIMM based on 32 pcs 64M x 4 DDR SDRAM 8K Refresh FEATURES • • • • • • • PIN ASSIGNMENT (Front View)

Contextual Info: MIXED TECHNOLOGY PUMA molate PUMA 2X0215 ISSUE 1.1 : October 1991 ADVANCE PRODUCT INFORMATION S e m ic o n d u c to r inc. 524,288 bit EEPROM and 524,288 bit SRAM Features Output user configurable as 8 / 16 bit wide. Average Power EEPROM 732 /1155 mW max .

MB86686A

Contextual Info: MB86683B Edition 1.0 1. OVERVIEW The NTC is a full duplex device which can be used to provide broadband termination functions in a variety of applications. Its primary use is for terminating the user or network ends of a user-network interface based on ITU-T,

marking C.S

Contextual Info: UG7128D65Q4LQ Data sheets can be downloaded at www.unigen.com 1G Bytes 128M x 64 bits SYNCHRONOUS DRAM MODULE 184 Pin DDR SDRAM Register & PLL DIMM based on 16 pcs 128M x 4 Stacked DDR SDRAM 8K Refresh FEATURES PIN ASSIGNMENT (Front View) • • • •

CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip

Abstract: CT2500 CT1698 mil-std-1397
Contextual Info: CT2500 MIL-STD-1397 Type D & E Low Level Serial Interface Protocol Chip Features • Performs Source and Sink functions CIRCUIT TECHNOLOGY www.aeroflex.com • Implements Type D & E protocols • Burst Mode Capability A E RO • Available in a PGA Package

T45 12H

Abstract: memory decoding 80386dx 16 bit sl90 LIM EMS 4.0 N804CS
Contextual Info: The FlexSet PC/AT 80386DX System & Memory Controller _ SL9352 PRELIMINARY FEATURES • 100% PC/AT Compatible. • Up to 20 MHz Performance. • ISA Bus Control Logic. • • • • • • Synchronous or Asynchronous System Control Operation.

A 434 RF Receiver TRANSMITTER PAIR

Abstract: AT45DB161B pam 8304 bcfk AUTOMATIC ROOM LIGHT CONTROLLER using ldr abstract AT91RM9200 SDRAM XC-01
Contextual Info: Features • Incorporates the ARM920T ARM Thumb® Processor • • • • • • • • • • • • • • • • – 200 MIPS at 180 MHz, Memory Management Unit – 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer – In-circuit Emulator including Debug Communication Channel

Contextual Info: HN62W5016N Series 524288-word x 32-bit/1048576-word x 16-bit CMOS MASK Programmable ROM HITACHI Preliminary Description The HN62W5016N is a 16-Mbit CMOS mask-programmable ROM organized either as 524,288-word by 32-bit or as 1,048,576-word by 16-bit. Realizing low power consumption, this memory is allowed for