D13 E1 Search Results

SN74ACT7803

Abstract: SN74ACT7805 SN74ACT7813 SN74ALVC7803 SN74ALVC7805 SN74ALVC7813
Contextual Info: SN74ALVC7803, SN74ALVC7805, SN74ALVC7813 512x 18, 256x 18, 64x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORIES SCAS436 - JUNE 1994 DL PACKAGE TOP VIEW Free-Running Read and Write Clocks Can Be Asynchronous or Coincident RESET D17 D16 D15 D14 D13 D12 D11 Read and Write Operations Synchronized to

marking E13 diode

Abstract: E13 diode problem 81C90 tcec SAE 81C90 PLCC28* STEP
Contextual Info: Microcontroller Division Errata Sheet Date / Release 07.06.99 / 1.0 Device: Stepping Code / Marking: Package: SAE 81C90/91 E13 PLCC-44/PLCC-28 This Errata Sheet describes the deviations from the current user documentation. The classification and numbering system is module oriented in a continual ascending sequence

DDX-4100A

Abstract: DDX-2060 DDX-4100 preamp with bass treble circuit diagrams subwoofer PREAMP circuit diagram subwoofer preamp DDX-2100 DDX2060 subwoofer ic type amplifier circuit diagram AC97
Contextual Info: DDX-4100A DDX Multichannel Digital Audio Processor FEATURES • • • • • • • • • • • • SOURCE-TO-SPEAKER INTEGRATED DIGITAL AUDIO SOLUTION WITH DDX-2060 POWER ICs DIGITAL PREAMP FUNCTIONS: • Digital Volume Control • Bass and Treble

LVDS83B

Abstract: SN65LVDS83B lvds83 SN75LVDS83B SN75LVDS83B routing signal generator rf marking Y2 24-bpc SN65LVDS83BZQL
Contextual Info: SN75LVDS83B www.ti.com . SLLS846 – MAY 2009 FLATLINK TRANSMITTER

Si4200-BM

Abstract: Si4200 SEN 1327 Si4133T-bm DCS 1800 RX SAW Filter Si4133T Si4201 SAFEK881MFL0T00R00 Si4201-BM transceiver gsm
Contextual Info: Aero A E R O T R A N S C E I V E R F O R GSM A N D G PR S WIRELESS COMMUNICATIONS Features Quad-band support: GSM 850 Class 4, small MS E-GSM 900 Class 4, small MS DCS 1800 Class 1 PCS 1900 Class 1 Si4200: 5 x 5 mm QFN32 Si4201: 4 x 4 mm QFN20 Si4133T: 5 x 5 mm QFN28

Z69D

Abstract: C106 C110 R101 R102 R104 R105 R106 R107 NB15h
Contextual Info: PARALLEL PORT A EXPA2 I EXPA1 I EXPAO I EXPB2 I EXPB1 I EXPBO I —^ IENB —^ SYNCD —— SYNCC —— SYNCB — E15 SYNCA - C H IP JD 3 PBACK C H IP JD 2 PBREQ FU CH IPJD 1 F15 CHIP I DO PBCH1 |LBCLKIN PBCHO|LBCLKOUT oooooooooooooooo „ R101 < R 1 0 2

AC97

Abstract: STA304A STA500 TQFP44
Contextual Info: STA304A DIGITAL AUDIO PROCESSOR WITH MULTICHANNEL DDX PRODUCT PREVIEW • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ STA304AEND TO END DIGITAL AUDIO INTEGRATED SOLUTION • DSP Functions: - DIGITAL VOLUME CONTROL - SOFT MUTE - BASS and TREBLE - PARAMETRIC EQ PER CHANNEL

Contextual Info: 19-5139; Rev 1; 3/11 KIT ATION EVALU E L B AVAILA Low-Power, High-Performance Dual I2S Stereo Audio Codec Ordering Information PART TEMP RANGE PIN-PACKAGE MAX9880AEWM+ -40°C to +85°C 48 WLP MAX9880AETM+ -40°C to +85°C 48 TQFN-EP* +Denotes a lead Pb -free/RoHS-compliant package.

SM320LF2407A-EP

Contextual Info: SM320LF2407AĆEP DSP CONTROLLERS SGUS036B − JULY 2003 − REVISED OCTOBER 2003 D Controlled Baseline D D D D D D D D D D D D D D D Two Event-Manager EV Modules − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of −55°C to 125°C

Contextual Info: SN75LVDS83A SLLS980D – JUNE 2009 – REVISED JUNE 2011 www.ti.com FLATLINK TRANSMITTER Check for Samples: SN75LVDS83A FEATURES 1 • 2 • • • • • • • • LVDS Display Serdes Interfaces Directly to LCD Display Panels with Integrated LVDS Package Options: 8.1mm x 14mm TSSOP

Contextual Info: TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP CONTROLLERS SPRS094E – APRIL 1999 – REVISED AUGUST 2000 D High-Performance Static CMOS Technology D D D D D External Memory Interface LF2407 – 33-ns Instruction Cycle Time (30 MHz) – 30 MIPS Performance

Voltage regulator 78 ML5

Abstract: SDI video mixer circuit diagram philips diode PH17 CS4205 CS4205-KQ F255 to generate 5v dc from 240 ac using 7805 CS-405
Contextual Info: CS4205 CrystalClear Audio Codec ’97 for Portable Computing l Three Features I2S l Integrated Asynchronous Input Port ZV Port l Integrated High-Performance Microphone Pre-Amplifier l Integrated Digital Effects Processing for Bass and Treble Response

IDH22

Abstract: LF2407 MCRC100 TMS320LF2407 instruction set 7432 encoder bldc motor control source code for TMS320 PIC stepper motor interfacing SPRs094 TMS320LC2404A 128Tc
Contextual Info: TMS320LF2407, TMS320LF2406, TMS320LF2402 DSP CONTROLLERS SPRS094F – APRIL 1999 – REVISED JANUARY 2001 D High-Performance Static CMOS Technology D D D D D – 33-ns Instruction Cycle Time 30 MHz – 30-MIPS Performance – Low-Power 3.3-V Design Based on TMS320C2xx DSP CPU Core

LVDS93

Contextual Info: SN65LVDS93A www.ti.com. SLLS992 – AUGUST 2009 FLATLINK TRANSMITTER

4352H

Abstract: CS4299 CS4299-JQ CS4299-KQ F255 sr3 caps
Contextual Info: CS4299 CrystalClear SoundFusion Audio Codec ’97 l AC ’97 2.1 Compatible l Industry Leading Mixed Signal Technology l 20-bit Stereo Digital-to-Analog Converters l 18-bit Stereo Analog-to-Digital Converters l Sample Rate Converters l Four Analog Line-level Stereo Inputs for

H-9 SMA

Abstract: F2407A instruction set
Contextual Info: TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 D High-Performance Static CMOS Technology D External Memory Interface LF2407A

f2407

Abstract: TMS320LC2402A TMS320LC2403A TMS320LC2404A TMS320LC2406A TMS320LF2402A TMS320LF2403A TMS320LF2406A TMS320LF2407A TMS320LF2407A CPU and Instruction Set
Contextual Info: TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A DSP CONTROLLERS SPRS145L − JULY 2000 − REVISED SEPTEMBER 2007 D High-Performance Static CMOS Technology D External Memory Interface LF2407A

RXB11

Abstract: SPRU282 TMS320C5xt 0741a 68-PL
Contextual Info: TMS320F243, TMS320F241 DSP CONTROLLERS SPRS064D − DECEMBER 1997 − REVISED FEBRUARY 2006 D High-Performance Static CMOS Technology D Includes the TMS320C2xx Core CPU D D D D D − Object-Compatible With the TMS320C2xx − Source-Code-Compatible With TMS320C25

Si4133-GT

Abstract: SI4133-D-GM Si4133-GM si4133-d-gt SI4112-D-GT SI4122DG Si4113 Si4122 Si4123 Si4133
Contextual Info: Si4133 Si4123/22/13/12 DUAL-BAND RF SYNTHESIZER WITH INTEGRATED VCOS FOR WIRELESS COMMUNICATIONS FEATURES Dual-band RF synthesizers RF1: 900 MHz to 1.8 GHz RF2: 750 MHz to 1.5 GHz IF synthesizer IF: 62.5 to 1000 MHz Integrated VCOs, loop filters, varactors, and resonators

MX23L3216XI-80

Abstract: MX23L3216 MX23L3216TI-10 MX23L3216TI-12 MX23L3216TI-80 MX23L3216XI-10 MX23L3216XI-12
Contextual Info: PRELIMINARY MX23L3216 32M-BIT MASK ROM FEATURES PIN DESCRIPTION • Bit organization - 4Mb x 8 byte mode - 2Mb x 16 (word mode) • Fast access time - Random access:80/25ns(max.) • Page Size - 8 words per page • Current - Operating:40mA - Standby:15uA(max.)

MT29F2G16AABWP

Abstract: LCDD0-LCDD23 Atmel touchscreen tx09d71vm1cca AT45D321 MT48LC16M16A2 at45d321c-cnc CCUSBA-32002-30X AT45DB321C AT45DB321C-CNC
Contextual Info: AT91SAM9261-EK Evaluation Board . User Guide AT91SAM9261-EK Evaluation Board User Guide 6198A–ATARM–15-Nov-05 Table of Contents Section 1 Overview. 1-1

PC intel 945 MOTHERBOARD schematic

Abstract: intel 945 motherboard schematic diagram RRUS 01 F54 regulator CS4297 CS4297-JQ CS4297-KQ CS4610 F255 pc 945 motherboard on board video output diagram schematic
Contextual Info: CS4297 Product Data Sheet = C IR R U S L O G IC FEATURES • AC’97 1.03 Compatible ■ Industry Leading Mixed Signal Technology CrystalClear SoundFusion ™ Audio Codec '97 ■ 18-bit stereo full-duplex Codec with fixed 48 kHz sampling rate ■ Four analog line-level stereo inputs for connec­

TLE2062

Abstract: TLV320AIC11 TLV320AIC11C TLV320AIC11I
Contextual Info: GeneralĆPurpose LowĆVoltage 1.1 V to 3.6 V I/O 16ĆBit 22ĆKSPS DSP CODEC TLV320AIC11 Data Manual 2002 HPA Product Group SLWS100A IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

TMC3211

Abstract: TMC3211H5C marking y27 3211H5C
Contextual Info: www.fairchildsemi.com TMC3211 Integer Divider 32-Bit, 20 MOPS Features • 32-bit by 16-bit fixed-point integer division with 32-bit quotient • 20 MHz clock rate and pipelined throughput rate • Three-bus I/O architecture allows unrestricted throughput