D0721 Search Results

40 pin lvds converter

Abstract: ADCLK854 cmos fan-out ADCLK854BCPZ JESD51-2 OUT10A CP-48-6 39 pin lvds converter
Contextual Info: 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS 1.2 GHz or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation)

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

Contextual Info: Data Sheet 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4

schematic dvd 686

Abstract: ADV3003 ADV3003ACPZ schematic diagram hdmi to analog audio IN26 dvi schematic HDMI to analog cable circuit diagram
Contextual Info: HDMI/DVI TMDS Equalizer ADV3003 FEATURES FUNCTIONAL BLOCK DIAGRAM PE_EN TX_EN PARALLEL CONTROL VTTI IP[3:0] IN[3:0] AVEE CONTROL LOGIC + 4 – 4 EQ BUFFER HIGH SPEED VTTO PE 4 + 4 – OP[3:0] ON[3:0] BUFFERED Figure 1. TYPICAL APPLICATION DIAGRAM HDTV SET

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9522-0 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

p627

Abstract: d07-15 P721 P621 P0629 d0715 P621 plastic package diode d0715 D0615 P628
Contextual Info: NEMA Terminal Blocks Medium Duty DESCRIPTION/APPLICATION This versatile series of Medium Duty blocks is available in two major categories: 300 volt 600 Series , and 600 Volt (700 Series). 600 & 700 SERIES 300 & 600 VOLT MEDIUM DUTY DESIGN ADVANTAGES • High circuit density - 183 circuits

AD9520

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2 GHz VCO AD9520-3 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

AD9520

Abstract: 569f
Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO AD9520-2 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVDS/24 CMOS Output Clock Generator AD9522-5 Preliminary Technical Data FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

d07-15

Contextual Info: BUCHANAN M E T R IC NEMA Terminal Blocks Catalog 1307612 Revised 7-01 700 Series, 600V M edium Duty, 0.375" Pitch jg fc A IT -A r ^ CHARACTERISTICS •HSieWr IS? 7 Direct M ount Flat Base Painted, Nylon Unpainted, Nylon Polypropylene : Channel Mount (Dovetail Base)

Contextual Info: HDMI/DVI TMDS Equalizer ADV3003 FUNCTIONAL BLOCK DIAGRAM FEATURES PE_EN TX_EN PARALLEL CONTROL VTTI IP[3:0] IN[3:0] AVEE CONTROL LOGIC + 4 – 4 VTTO BUFFER EQ PE HIGH SPEED 4 + 4 – OP[3:0] ON[3:0] BUFFERED Figure 1. TYPICAL APPLICATION DIAGRAM HDTV SET

p627

Abstract: d07-15 D0721 D0715 p730 p727 P0627 P729 p0629 p721
Contextual Info: NEMA Terminal Blocks Medium Duty DESCRIPTION/APPLICATION This versatile series of Medium Duty blocks is available in two major categories: 300 volt 600 Series , and 600 Volt (700 Series). 600 & 700 SERIES 300 & 600 VOLT MEDIUM DUTY DESIGN ADVANTAGES • High circuit density - 183 circuits

Contextual Info: f i | Product Description Features and Modes of Operation This specification describes the Bt8510 E l (often called CEPT or DS1A frame synchronization, signal generation, and recovery circuit for application in digital terminal interfaces operating at 2.048 Mb/s. Applications for this device include

Contextual Info: SERIAL ACCESS SPI BUS 4K 512x8 EEPROM • 100,000 ERASE/WRITE CYCLES ■ 10 YEARS DATA RETENTION ■ SINGLE 4.5V to 5.5V SUPPLY VOLTAGE ■ SPI BUS COMPATIBLE SERIAL INTERFACE ■ 2 MHz CLOCK RATE MAX - BLOCK WRITE PROTECTION ■ STATUS REGISTER - 16 BYTE PAGE MODE

Sine Wave Generator stp 2740

Abstract: AD9522 OUT10A
Contextual Info: 12 LVDS/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9522-0 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

AD9520

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.8 GHz VCO AD9520-0 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.2 GHz VCO AD9520-2 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 1.6 GHz VCO AD9520-4 FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

Contextual Info: 1.8 V, 12-LVDS/24-CMOS Output, Low Power Clock Fanout Buffer ADCLK854 FEATURES FUNCTIONAL BLOCK DIAGRAM 2 selectable differential inputs Selectable LVDS/CMOS outputs Up to 12 LVDS 1.2 GHz or 24 CMOS (250 MHz) outputs <12 mW per channel (100 MHz operation)

AD9520-1

Abstract: intel i9 AD9520
Contextual Info: 12 LVPECL/24 CMOS Output Clock Generator with Integrated 2.5 GHz VCO AD9520-1 APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Forward error correction G.710

p627

Abstract: P721 d07-15 diode d0715 P621 P628 P624 D725 D0715 0730
Contextual Info: Data downloaded from http://www.anglia.com - the website of Anglia - tel: 01945 474747 NEMA Terminal Blocks METRIC Catalogue 1654741 Revised 1-04 Dimensions are millimetres over inches 600 & 700 Series, 300 & 600 Volt Medium Duty DESCRIPTION/APPLICATION This versatile series of Medium Duty

Contextual Info: FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10GFC, Synchronous Ethernet, OTU2/3/4 Forward error correction G.710 Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs

0720l

Abstract: ST95010 MS08 ST9501
Contextual Info: SERIAL ACCESS SPI BUS 1K 128 x 8 EEPROM • ■ ■ ■ ■ ■ ■ ■ ■ ■ 100,000 ERASE/WRITE CYCLES 10 YEARS DATA RETENTION SINGLE 4.5V to 5.5V SUPPLY VOLTAGE SPI BUS COMPATIBLE SERIAL INTERFACE 2 MHz CLOCK RATE MAX BLOCK WRITE PROTECTION STATUS REGISTER