CYPRESS FLASH 373 Search Results

nitto 201

Abstract: JESD22 cy7c373 nittomp8000 KC700 reliability test data CY7C374I-JC
Contextual Info: Cypress Semiconductor Qualification Report QTP# 96471/96472 V 2.0 May, 1997 UltraLogic 64-Macrocell Flash CPLD CY7C372I/373I Cypress Semiconductor UltraLogic 64-Mcell Flash CPLD Device: CY7C372I/373I Package: 44-pin PLCC QTP# 96471/96472 Version 2.0 Page 2 of 8

cypress flash 370 CPLD

Abstract: features cypress flash 370 logic block diagram of cypress flash 370 device cypress flash 370 0117C
Contextual Info: 400-943-Z843-> 07/31/95 B9'i B7'ì Z7 16838B01932 Cypress Seniconducto Page B2B 7C37S: W ednesday September 23,1092 Revtalon: Thurvdty, June 1 8 ,1 M 4 CYPRESS 64-Macrocell Flash CPLD den q»ed delays such as fanout effects, in­ terconnect delays, or expander delays. Re­

Contextual Info: W CYPRESS CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Functional Description Features • • • • 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology — JTAG interface

Contextual Info: fax id: 6138 CY7C373Î ^CYPRESS UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram mable ISR™ Flash technology

CY7C372

Abstract: CY7C373 EME-6300H
Contextual Info: Qualification Report January 1996, QTP# 95508, Version 1.0 64-Macrocell Flash CPLD CY7C372/373 PRODUCT DESCRIPTION (for qualification) Information provided in this document is intended for generic qualification and technically describes the Cypress part supplied:

CY7C374

Abstract: CY7C375 FLASH370 IEEE-STD-1076 architecture of cypress FLASH370 cpld
Contextual Info: CPLD Family FLASH370 UltraLogic™ High-Density Flash CPLDs Features General Description • Flash erasable CMOS CPLDs The FLASH370™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled performance. Each member of the family is designed with Cypress’s state-of-the-art Flash technology. All of the devices are

Contextual Info: fax id: 6138 CYPRESS PRELIMINARY CY7C373Ì UltraLogic 64-Macrocell Flash CPLD Features • • • • Functional Description 64 macrocells in four logic blocks 64 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogram m able ISR™ Flash technology

architecture of cypress FLASH370 cpld

Abstract: FLASH370TM architecture of cypress FLASH370 device CY7C374 CY7C375 FLASH370 architecture of cypress FLASH370 cpld with figure
Contextual Info: 70 CPLD Family FLASH370™ UltraLogic™ High-Density Flash CPLDs Features General Description • Flash erasable CMOS CPLDs The FLASH370™ family of CMOS CPLDs provides a range of high-density programmable logic solutions with unparalleled performance. Each member of the family is designed with Cypress’s state-of-the-art Flash technology. All of the devices are

Contextual Info: CY7C373Ì ADVANCED INFORMATION m r CYPRESS UltraLogic 64-Macrocell Flash CPLD Features FLASH370i™ family o f high-density, high­ • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR

Contextual Info: CYPRESS 64-Macrocell Flash CPLD is designed to bring the ease of use and high performance of the 22V10 to higbdensity CPLDs. Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays

Contextual Info: W CYPRESS CY7C374Ì UltraLogic 128-Macrocell Flash CPLD Functional Description Features • 128 m a cro c ells in eig h t logic blocks • 64 I/O pins • 5 d ed icated inp u ts inclu d in g 4 clo c k pins • In-S ystem R e p ro g ra m m ab le IS R ™ Flash te c h n o lo g y

Contextual Info: CY7C373 PRELIMINARY CYPRESS SEMICONDUCTOR Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f\lAX = 100 MHz — tpD = 12 ns — ts - 9 ns — tco = 9 ns • Electrically alterable Flash

tlO41

Abstract: 7C373-125 CY7C373 CY7C374 FLASH370 Wo2c
Contextual Info: CYPRESS Features • 64 macrocells in four logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M A X = 12S MHz — tpo = 10 ns — ts = 5.5 ns — tc o = 6-5 ns • Electrically alterable Flash

Contextual Info: CY7C374 PRELIMINARY y CYPRESS 128-Macrocell Flash CPLD Features • 128 macrocells in eight logic blocks • 64 I/O pins • 6 dedicated inputs including 4 clock pins • No hidden delays • High speed — f M AX = 100 MHz — tpo = 12 ns — ts = 7 ns — t c o = 7 ns

cypress flash 370 CPLD

Contextual Info: F la s h 3 7 0 i ISR ™ W CYPRESS ADVANCED i n f o r m a t i o n CPLD Family UltraLogic ™ High-Density Flash CPLDs Features • Warp2 !Warp2 + — Low-cost, text-based design tool, PLD compiler — IEEE 1164-compliant VHDL — Available on PC, Sun, and HP plat­

Contextual Info: O T / OC5 /0 5 :» /» ^ R e v is io n : J u n e 24, 1996 CY7C373 rw CYPRESS UltraLogic 64-M acrocell Flash CPLC F la s h 370 fam ily, the C Y 7 C 3 73 is designed to bring the ease of use and high p e rfo rm an ce of th e 2 2 V 10 to h ig h -d e n s ity

319s2

Contextual Info: ¿? CYPRESS CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional D escription • 6 4 m acrocells in fou r logic blocks • 6 4 I/O pins • 6 d ed icated in p u ts in clu d in g 4 clock p in s • N o h id d en delays T h e C Y 7 C 3 7 3 is a F lash e ra s a b le C o m p lex

architecture of cypress FLASH370 cpld

Abstract: cypress 22V10 architecture of cypress FLASH370 device Cypress Semiconductor CY7C373 CY7C374 FLASH370 cypress flash 373 architecture of cypress FLASH370 flash erasable cpld
Contextual Info: 373 For new designs see CY7C373i CY7C373 UltraLogic 64-Macrocell Flash CPLD Features Functional Description • 64 macrocells in four logic blocks The CY7C373 is a Flash erasable Complex Programmable Logic Device CPLD and is part of the FLASH370TM family of

Contextual Info: CY8C21345/CY8C21645 CY8C22345/CY8C22345H/CY8C22645 Automotive PSoC Programmable System-on-Chip Automotive PSoC ® Programmable System-on-Chip™ Features ❐ • Automotive Electronics Council AEC Q100 qualified Powerful Harvard-architecture processor

Contextual Info: CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC Programmable System-on-Chip Automotive PSoC ® Programmable System-on-Chip™ Features Automotive Electronics Council AEC Q100 qualified Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz

Contextual Info: CY8C21345, CY8C21645 CY8C22345, CY8C22345H, CY8C22645 Automotive PSoC Programmable System-on-Chip Automotive PSoC ® Programmable System-on-Chip™ Features ❐ • Automotive Electronics Council AEC Q100 qualified Powerful Harvard-architecture processor

features cypress flash 370

Abstract: logic block diagram of cypress flash 370 device cypress flash 370 device cypress flash 370 cypress flash 370 technology cypress FLASH370 device cypress quickpro II cypress flash 370 device technology
Contextual Info: F la s h 3 7 0 T0 CYPRESS — Low-cost, text-based design tool, PLD compiler — IEEE 1076-compliant VHDL — Available on PC and Sun platforms • Warp3m CAE development system — VHDL input — ViewLogic graphical user interface — Schematic capture ViewDraw

flash370i

Abstract: FLASH370 architecture of cypress FLASH370 cpld
Contextual Info: fax id: 6135 y FLASH370i ISR™ CPLD Family UltraLogic™ High-Density Flash CPLDs Features • Flash In-System Reprogrammable ISR™ CMOS CPLDs — Combines on board reprogramming with pinout flexibility and a simple timing model — Design changes don’t cause pinout or timing changes

FLASH370

Abstract: 106373
Contextual Info: amily FLASH370i ISR™ CPLD Family UltraLogic™ High-Density Flash CPLDs Features — No expander delays • Flash In-System Reprogrammable ISR™ CMOS CPLDs — Combines on board reprogramming with pinout flexibility and a simple timing model — Design changes don’t cause pinout or timing changes