CY7C37H Search Results

Contextual Info: w ~ CYPRESS Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable ISR Flash technology — JTAG interface • No hidden delays • High speed — f M A X = 143 MHz — tpD= 8*5 ns

l83A

Contextual Info: fax id: 6136 C Y7C371 i p vp v « *1 X X UltraLogic 32-Macrocell Flash CPLD Features • 32 m a croc e lls in two logic b lo c ks • 32 I/O pin s • 5 dedicated inp u ts in c lu d in g 2 clock pins • In-System R e p ro gram m a b le ISR™ Flash te ch n o lo g y

cypress flash 370 CPLD

Contextual Info: F la s h 3 7 0 i ISR ™ W CYPRESS ADVANCED i n f o r m a t i o n CPLD Family UltraLogic ™ High-Density Flash CPLDs Features • Warp2 !Warp2 + — Low-cost, text-based design tool, PLD compiler — IEEE 1164-compliant VHDL — Available on PC, Sun, and HP plat­

cypress flash 370

Contextual Info: '#C YPR ESS ADVANCED INFORMATION CY7C371Ì UltraLogic 32-Macrocell Flash CPLD Features • 32 macrocells in two logic blocks • 32 I/O pins • 6 dedicated inputs including 2 clock pins • In-System Reprogrammable 1SR " Flash technology — JT A (i interface

Contextual Info: PRELIMINARY CYPRESS UltraLogic 32-Macrocell Flash CPLD Device CPLD and is part of the FLASH370i “ family of high-density, high­ speed CPLDs. Like all members of the FLASH370i family, the CY7C371i is de­ signed to bring the ease of use and high performance of the 22V10, as well as PCI