CY7C330 Search Results

Contextual Info: CY7C330 C Y P R E S S •0 Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi­ plexer — feed back multiplexer — output enable OE multiplexer • All twelve macrocell state registers

CY7C330

Contextual Info: fax id: 6019 1CY 7C33 0 CY7C330 CMOS Programmable Synchronous State Machine • 66-MHz operation — 3-ns input set-up and 12-ns clock to output Features • Twelve I/O macrocells each having: — registered, three-state I/O pins — 15-ns input register clock to state register clock

Contextual Info: CY7C330 / CYPRESS Features • TVvelve I/O macrocells each having: — registered, three-state I/O pins — input register clock select multi* plexer — feed back multiplexer — output enable OE multiplexer • AH twelve macrocell state registers can be hidden

Contextual Info: CY7C330 '# C Y P R E S S CMOS Programmable Synchronous State Machine Three separate clocks— two inputs, one output Common pin 14-co n tro lled or product term —controlled output en­ able for each I/O pin 256 product terms—32 per pair of macrocells, variable distribution

Contextual Info: CY7C330 CYPRESS SEMICONDUCTOR CMOS Programmable Synchronous State Machine Features • 12 I / O m acro cells each having: — registered, three-state I /O pins — input register clock select m ultiplexer — feed back m ultiplexer — output enable O E

L496D

Abstract: 9l reset CY7C331 ST L11922 0423-J
Contextual Info: CY7C331 -W C Y P R E S S Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coining from the I/O pin — Independent product term set,

Contextual Info: Asynchronous Registered EPLD 13 inputs, 12 feedback VO pins, plus 6 shared I/O macrocell feedbacks for a total of 31 true and complementary inpnts High speed: 20 ns maximum tpo Security bit Space-saving 28-pin slim-line DIP package; also available in 28-pin

Contextual Info: fax id: 6018 CY7C335 Universal Synchronous EPLD — 2-ns input set-up and 9-n s o u tp u t re g is te r clo c k to o u tp u t Featu res • 1 0 0-M H z o u tp u t registered o peration — 10-ns inp u t re g is te r clo ck to sta te re g is te r clo ck • Tw elve I/O m acrocells, each having:

transistor c331

Abstract: c331 transistor C3318 C3317 C331 C3311 C331 datasheet CY7C331 20HC c331 equivalent
Contextual Info: CY7C331 Asynchronous Registered EPLD Features • Low power — 90 mA typical ICC quiescent • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — 180 mA ICC maximum — UV-erasable and reprogrammable — One feedback flip-flop with input coming from the

C3357

Abstract: c3358 CERAMIC LEADLESS CHIP CARRIER diode c335 c3356 c3355 C335 CY7C335-66PC CY7C335 C3354
Contextual Info: fax id: 6018 1CY 7C33 5 CY7C335 Universal Synchronous EPLD Features — 2-ns input set-up and 9-ns output register clock to output • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — 10-ns input register clock to state register clock

TCO - 909 F 10 MHz

Abstract: TCO - 909 F CERAMIC LEADLESS CHIP CARRIER C335 CY7C335
Contextual Info: CY7C335 CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer — Feed back multiplexer — Output enable OE multiplexer

CY62256LL-PC

Abstract: VIC068A-GC VIC64-NC VIC64-UMB PALCE22V10-JI PALC16L8Q PLD VME A113 CY7B923 JESD22-A113
Contextual Info: Cypress Semiconductor Product Reliability 1997 Published June, 1997 CYPRESS SEMICONDUCTOR PRODUCT RELIABILITY TABLE OF CONTENTS 1.0 OVERVIEW OF CYPRESS SEMICONDUCTOR TOTAL QUALITY MANAGEMENT SYSTEM. 1 2.0 ELECTRICAL AVERAGE OUTGOING QUALITY. 2

C3317

Abstract: L1190 CY7331
Contextual Info: Asynchronous Registered EPLD Features • TWelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock inputs on all

Contextual Info: CY7C332 CYPRESS Features • 12 I/O macrocells each having: — Registered, latched, or transparent array input — A choice of two clock sources — Global or local output enable OE — Up to 19 product term s (PTs) per output — Product term (PT) output polarity

Contextual Info: _ CY7C335 Universal Synchronous EPLD SEMICONDUCTOR Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect multiplexer

c677

Contextual Info: I U J O J . / / 1 0 /9 1 Revision: Friday, March 2 6 ,1993b M fP ? 1993 CY7C335 7J s CYPRESS SEMICONDUCTOR Universal Synchronous EPLD construct very high performance state ma­ chines. The architecture of the CY7C335, consist­ ing of the user-configurable output macrocell, bidirectional I/O capability, input reg­

Contextual Info: CY7C335 / CYPRESS Features • 100-MHz output registered operation • Twelve I/O macrocells, each having: — Registered, three-state I/O pins — Input and output register clock se­ lect m ultiplexer — Feed back multiplexer — Output enable OE multiplexer

C3325

Abstract: l9618 L9680 C3326 L9622 l9742 tunel C3321
Contextual Info: C YP RE SS SEMICONDUCTOR a ML.E D 2S 0^bb2 GQQ7Q33 S Q C Y P "T" ^ ^ CYPRESS SEMICONDUCTOR CY7C332 Registered Combinatorial EPLD 13 input macrocells, each having: — Complementary input — Register, latch, or transparent access — I\vo clock sources 15 ns tpo max.

Device-List

Abstract: NEC D2716D novatek nt68f63 nt68f63 NEC D2732D D2716D 16V8H-25 ATMEL 220 24C16 D2732D 16V8H-15
Contextual Info: LabTool-48 Version 4.67 <ALL> Device List Page 1 of 20 ACTRANS AC29LV400B *44PS AC29LV400B *48TS AC29LV400T *44PS AC29LV400T *48TS ALi M6759 M6759 *44 M6759 *44Q M8720 Alliance AS29F040 AS29LV800T *48TS AS29LV800B *44PS AS29LV800B *48TS AS29LV800T *44PS Altera

L9806

Abstract: L9626 L9630 c3328 L9642 L9646 L5650 L9823 L9680 CY7C332-15HC
Contextual Info: V 12 I/O raacrocells each having: — Registered, latched, or transparent array input — A choice o f two clock sources — Global or local output enable OE — Up to 19 product terms (PTs) per output — Product term (PT) output polarity control • 192 product terms with variable

cy3341

Abstract: 64K X 4 CACHE SRAM CY7C190 pasic380 cy7c189 palce22v10 programming guide palce16v8 programming algorithm STATIC RAM 6264 vhdl code for 8-bit parity checker 64x18 synchronous sram
Contextual Info: Product Selector Guide Static RAMs Organization/Density Density X1 X4 X4 SIO 7C147 2147 7C123 7C148 7C149 7C150 7C189 7C190 2148 2149 7C122 9122 93422 7C167A 7C168A 7C169A 7C170A 7C171A 7C172A 7C128A 7C187 7C164 7C166 7C161 7C162 7C185 6264 7C182 7C197 7C194

61S11

Contextual Info: fax id: 6016 CY7C331 CYPRESS Asynchronous Registered EPLD Features • Twelve I/O macrocells each having: — One state flip-flop with an XOR sum-of-products input — One feedback flip-flop with input coming from the I/O pin — Independent product term set, reset, and clock in­

CY27S03A

Abstract: 15JC10 CY7C190 cy7c9101 cy7c122 die VIC068A user guide
Contextual Info: Thermal Management and Component Reliability slope of the logarithmic plots is given by the activation energy of the failure mechanisms causing thermally activated wear out of the device see Figure 1 . One of the key variables determining the long-term reliability

NEC D2732D

Abstract: nt68f63 novatek nt68f63 d2716d NEC D2716D atc 93lc46 D2732D CIRCUIT NEC D2716D TMS87C510 16V8H-25
Contextual Info: Dataman-48 Version 4.30 <ALL> Device List ALi M6759 www.dataman.com M6759 *44 M6759 *44Q M8720 AS29LV800B *44PS AS29LV800B *48TS AS29LV800T *44PS Altera EP1210 EP220 EP312 EP330 EP900 EP910-T EPC1064 EPC1213 EPC1441 as 1213 EPM3064A *44 EPM5192 @84 EPM7032AEas7032 *44