CY7C167 Search Results

C167A-3

Abstract: C167A-2 CY7C167A CY7C167A-35DMB cy7c167a-35pc
Contextual Info: CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

CY7C167A

Abstract: CY7C167A-35DMB
Contextual Info: CY7C167A '0 CYPRESS 16K x 1 Static RAM Features Functional D escription • Automatic power-down when dese­ lected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

C167A

Abstract: C167A-2 C167A-3 CY7C167A CY7C167A-35VC
Contextual Info: 1CY 7C16 7A CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

electrostat

Contextual Info: CY7C 167A CYPRESS 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed The CY7C167A is a high-performance CMOS static RAM or­ ganized as 16,384 words by 1 bit. Easy memory expansion is

Contextual Info: Data Sheet March 1992 l ^ AT&T Microelectronics ATT7C167 High-Speed CMOS SRAM 16 Kbits 16K x 1 , Separate I/O Features • High speed — 10 ns maximum access time ■ Plug-compatible with IDT6167 and CY7C167 ■ Automatic powerdown during long cycles ■ Low-power operation

C167A-2

Abstract: CY7C167A
Contextual Info: CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 495 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

C167A-2

Abstract: CY7C167A
Contextual Info: CY7C167A 16K x 1 Static RAM Features D Functional Description The CY7C167A is a highĆperformance CMOS static RAM organized as 16,384 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable CE and threeĆstate drivers. The CY7C167A has an automatic powerĆdown

CY7C128A SRAM

Abstract: 256K x 8 SRAM CY7C128A SRAM CY7C128A CY7C167A CY7C168A CY7C169A CY7C170A CY7C171A CY7C172A EME-6300H
Contextual Info: Qualification Report December, 1994, QTP# 94065 Version 1.0 16K SRAM, 7% SHRINK, R21 TECHNOLOGY MARKETING PART NUMBER DEVICE DESCRIPTION CY7C128A 2K x 8 Static R/W RAM CY7C167A 16K x 1 Static R/W RAM CY7C168A 4K x 4 Static RAM CY7C169A 4K x 4 Static RAM CY7C170A

Contextual Info: CY7C167A f ^ Y P P P 'c c Features Functional Description • Automatic power-down when dese­ lected T h e C Y 7C167A is a high-perform ance CM O S static R A M organized as 16,384 w ords by 1 bit. Easy m em ory expansion is provided by an active LO W chip enable

C167A-2

Abstract: CY7C167A
Contextual Info: 67A CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 495 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

3M Touch Systems

Contextual Info: CY7C1661KV18, CY7C1676KV18 CY7C1663KV18, CY7C1665KV18 144-Mbit QDR II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit QDR ® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations Separate independent read and write data ports

CY7C167A

Abstract: Zl81
Contextual Info: CY7C167A '0 CYPRESS 16K x 1 Static RAM Features Functional Description • Automatic power-down when dese­ lected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

Contextual Info: CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 144-Mbit density (8 M x 18, 4 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: Data Sheet January 1992 g^A T& T ^ ^ ^ M ic ro e le c tro n ic s ATT7C167 High-Speed CMOS SRAM 16 Kbits 16K x 1 , Separate I/O Features • High speed— 10 ns maximum access time ■ Plug-compatible with IDT6167 and CY7C167 ■ Automatic powerdown during long cycles

Contextual Info: CY7C167 CYPRESS SEMICONDUCTOR Features Functional Description • Automatic power-down when dese­ lected • CMOS for optimum speed/power • Highspeed — 25 ns • Low active power — 275 mW • Low standby power — 83 mW • TTL-compatible inputs and outputs

CY7C167A

Contextual Info: CY7C167A 16K x 1 Static RAM Features Functional Description The CY7C167A is a high-performance CMOS static RAM or­ ganized as 16,384 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable CE and three-state drivers. The CY7C167A has an automatic power-down fea­

7C167

Contextual Info: CY7C167 CYPRESS SEMICONDUCTOR Features Functional Description • Automatic power-down when d ese­ lected T he CY 7C167 is a high-perform ance C M O S static RA M organized as 16,384 w ords by 1 bit. Easy m em ory expansion is provided by an active LO W chip enable

C167A-3

Abstract: C167A-2 CY7C167A
Contextual Info: 67A CY7C167A 16K x 1 Static RAM Features Functional Description • Automatic power-down when deselected • CMOS for optimum speed/power • High speed — 15 ns • Low active power — 495 mW • Low standby power — 220 mW • TTL-compatible inputs and outputs

v 2164

Abstract: CY7C167A-35VC
Contextual Info: CY7C167A SEMICONDUCTOR 16,384 x 1 Static RAM Features Functional Description • Automatic power-down when dese­ lected • CMOS for optim um speed/power • High speed — 15 ns T he CY7C167A is a high-performance CMOS static RAM organized as 16,384 words by 1 bit. Easy memory expansion is

CY7C167A-35DMB

Contextual Info: CY7C167A CYPRESS SEMICONDUCTOR Features Functional Description • Automatic power-down when dese­ lected • CMOS for optimum speed/power • High speed — 15 ns • Low active power The CY7C167A is a high-performance CMOS static RAM organized as 16,384

Contextual Info: CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture 2.5 Cycle Read Latency 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 144-Mbit density (8 M x 18, 4 M × 36) With Read Cycle Latency of 2.5 cycles:

Contextual Info: _ CY7C167 SEMICONDUCTOR 16,384 x 1 Static R/W RAM Features F u nctional D escription • Automatic power-down when dese­ lected • CMOS for optimum speed/power T h e CY7C167 is a high-perform ance C M O S static R A M organized as 16,384

329u

Contextual Info: CY7C167A CYPRESS SEMICONDUCTOR 16,384 x 1 Static RAM Functional Description Features Automatic power-down when dese­ lected CMOS for optimum speed/power High speed — 15 ns Low active power — 275 mW Low standby power — 83 mW TTL-compatible inputs and outputs

7c167

Abstract: 6153A
Contextual Info: CY7C167 CYPRESS SEMICONDUCTOR 16,384 x 1 Static R/W RAM Features Functional Description • Automatic power-down when dese­ lected • CMOS for optimum speed/power • High speed - 25 ns T h e CY 7C167 is a high-perform ance C M O S static R A M organized as 16,384