CY7C1298H Search Results

CY7C1298H Datasheets (4)

Part	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1298H	Cypress Semiconductor	1-Mbit (64K x 18) Pipelined DCD Sync SRAM	Original	PDF	383.3KB	16
CY7C1298H-100AXC	Cypress Semiconductor	1-Mbit (64K x 18) Pipelined DCD Sync SRAM	Original	PDF	383.31KB	16
CY7C1298H-100AXI	Cypress Semiconductor	1-Mbit (64K x 18) Pipelined DCD Sync SRAM	Original	PDF	383.29KB	16
CY7C1298H-133AXC	Cypress Semiconductor	1-Mbit (64K x 18) Pipelined DCD Sync SRAM	Original	PDF	383.31KB	16

Catalog Datasheet	Type	Document Tags	PDF
CY7C1298H Abstract: CY7C1298H-100AXC Contextual Info: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture	Original	CY7C1298H 18-bit 166-MHz 100-Pin CY7C1298H CY7C1298H-100AXC	PDF
Contextual Info: CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture	Original	CY7C1298H 18-bit 166-MHz 100-Pin	PDF
Contextual Info: PRELIMINARY CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture	Original	CY7C1298H 18-bit 166-MHz 133-MHz 100-pin CY7C1298H	PDF
Contextual Info: PRELIMINARY CY7C1298H 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture	Original	CY7C1298H 18-bit 166-MHz 133-MHz 100-pin CY7C1298H	PDF