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    CY7C1298F Search Results

    CY7C1298F Datasheets (2)

    Part ECAD Model Manufacturer Description Datasheet Type PDF PDF Size Page count
    CY7C1298F
    		Cypress Semiconductor 1-Mb (64K x 18) Pipelined DCD Sync SRAM Original PDF 336.28KB 15
    CY7C1298F-133AC
    		Cypress Semiconductor 1-Mb (64K x 18) Pipelined DCD Sync SRAM Original PDF 336.28KB 15
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    CY7C1298F Price and Stock

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    Rochester Electronics LLC CY7C1298F-133AC

    STANDARD SRAM, 64KX18, 4NS, CMOS
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    DigiKey CY7C1298F-133AC Bulk 19
    • 1 -
    • 10 -
    • 100 $16.38
    • 1000 $16.38
    • 10000 $16.38
    		Buy Now

    Cypress Semiconductor CY7C1298F-133AC

    CY7C1298F-133AC
    Distributors Part Package Stock Lead Time Min Order Qty Price Buy
    Verical () CY7C1298F-133AC 398 25
    • 1 -
    • 10 -
    • 100 $18.70
    • 1000 $16.74
    • 10000 $15.75
    		Buy Now
    CY7C1298F-133AC 177 25
    • 1 -
    • 10 -
    • 100 $18.70
    • 1000 $16.74
    • 10000 $15.75
    		Buy Now
    Rochester Electronics CY7C1298F-133AC 575 1
    • 1 -
    • 10 -
    • 100 $14.96
    • 1000 $13.39
    • 10000 $12.60
    		Buy Now

    CY7C1298F Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    Contextual Info: CY7C1298F 1-Mb 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F PDF

    A101

    Abstract: CY7C1298F CY7C1298F-133AC
    Contextual Info: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F A101 CY7C1298F-133AC PDF

    A101

    Abstract: CY7C1298F CY7C1298F-133AC
    Contextual Info: CY7C1298F 1-Mbit 64K x 18 Pipelined DCD Sync SRAM Functional Description[1] Features • Registered inputs and outputs for pipelined operation • Optimal for performance (Double-Cycle deselect) — Depth expansion without wait state • 64K x 18-bit common I/O architecture


    Original     		CY7C1298F 18-bit 166-MHz 133-MHz 100-pin CY7C1298F A101 CY7C1298F-133AC PDF