CY7C1256AV18 Search Results

FBGA-15

Contextual Info: CY7C1243V18 CY7C1245V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 375 MHz clock for high bandwidth

Contextual Info: CY7C1276V18 CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth

Contextual Info: CY7C1256V18 CY7C1243V18 CY7C1245V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate Independent Read and Write data ports With Read Cycle Latency of 2.0 cycles: — Supports concurrent transactions

CY7C1263V18

Abstract: CY7C1261V18 CY7C1265V18 CY7C1276V18
Contextual Info: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.5 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions

CY7C1241V18

Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18
Contextual Info: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,

CY7C1263V18-400

Contextual Info: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,

CY7C1261V18

Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18
Contextual Info: CY7C1261V18 CY7C1276V18 CY7C1263V18 CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1261V18, CY7C1276V18, CY7C1263V18, and CY7C1265V18 are 1.8V Synchronous Pipelined SRAMs,

Contextual Info: CY7C1241V18 CY7C1256V18 CY7C1243V18 CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Functional Description • Separate independent read and write data ports The CY7C1241V18, CY7C1256V18, CY7C1243V18, and CY7C1245V18 are 1.8V Synchronous Pipelined SRAMs,

CY7C1261V18

Abstract: CY7C1263V18 CY7C1265V18 CY7C1276V18
Contextual Info: CY7C1261V18, CY7C1276V18 CY7C1263V18, CY7C1265V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features • Configurations With Read Cycle Latency of 2.0 cycles: Separate independent read and write data ports ❐ Supports concurrent transactions

CY7C1241V18

Abstract: CY7C1243V18 CY7C1245V18 CY7C1256V18
Contextual Info: CY7C1241V18, CY7C1256V18 CY7C1243V18, CY7C1245V18 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles:

Contextual Info: CY7C1263V18 CY7C1265V18 PRELIMINARY 36-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth