CY7C1165V18 Search Results

CY7C1165V18 Datasheets (2)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1165V18		Cypress Semiconductor	18-Mbit QDR-II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)	Original	PDF	1.01MB	29
CY7C1165V18-400BZXC		Cypress Semiconductor	Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 400MHZ 165FBGA	Original	PDF		29

CY7C1165V18 Price and Stock

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Cypress Semiconductor


Cypress Semiconductor CY7C1165V18-400BZXC CY7C1165V18-400BZXC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	CY7C1165V18-400BZXC		381		25	1 - 10 - 100 $62.35 1000 $55.79 10000 $52.50	Buy Now

CY7C1165V18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06582 Spec Title: CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT QDR TM -II+ SRAM 4-WORD BURST ARCHITECTURE (2.5 CYCLE READ LATENCY) Sunset Owner: Jayasree Nayar (njy) Replaced by: NONE CY7C1161V18, CY7C1176V18	Original	CY7C1161V18/CY7C1176V18/CY7C1163V18/ CY7C1165V18, 18-MBIT CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18	PDF
Contextual Info: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18, CY7C1176V18, CY7C1163V18, CY7C1165V18	PDF
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Contextual Info: CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18 CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18	PDF
Contextual Info: CY7C1176V18 CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1176V18 CY7C1163V18 CY7C1165V18 18-Mbit CY7C1176V18/CY7C1163V18/CY7C1165V18 CY7C1176BV18	PDF
CY7C1161V18 Abstract: CY7C1163V18 CY7C1165V18 CY7C1176V18 Contextual Info: CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1161V18, CY7C1176V18 CY7C1163V18, CY7C1165V18 18-Mbit CY7C1161V18 CY7C1163V18 CY7C1165V18 CY7C1176V18	PDF
Contextual Info: CY7C1163V18 CY7C1165V18 PRELIMINARY 18-Mbit QDR -II+ SRAM 4-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1163V18 CY7C1165V18 18-Mbit	PDF