CY7C1046 Search Results

c1046

Contextual Info: V CYPRESS ADVANCED INFORMATION CY7C1046 1M x 4 Static RAM Features sion is provided by an active LO W C hip Enable CE , an active LO W O utput Enable (O E), and th re e -sta te drivers. W riting to th e de vice is a c c o m plished by ta kin g C hip Enable (CE) and

CY7C1046BV33

Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Contextual Info: 046BV33 PRELIMINARY CY7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

Contextual Info: CY7C1046DV33 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046CV33 • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS standby power — ISB2 = 10 mA • 2.0 V data retention

Contextual Info: CY7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description The CY7C1046D[1] is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW

CY7C1046BV33

Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Contextual Info: 33 PRELIMINARY CY7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

CY7C1046V33

Abstract: CY7C1046V33-12VC CY7C1046V33-15VC
Contextual Info: 3 ADVANCE INFORMATION CY7C1046V33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention)

CY7C1046

Abstract: 7c1046
Contextual Info: ADVANCED INFORMATION CY7C1046 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1018 mW max. • Low CMOS standby power(L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

Contextual Info: CY7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power

Contextual Info: CY7C1046DV33 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046CV33 • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS standby power — ISB2 = 10 mA • 2.0 V data retention

CY7C1046CV33

Abstract: CY7C1046DV33 CY7C1046DV33-10VXI 30592
Contextual Info: CY7C1046DV33 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description The CY7C1046DV33[1] is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an

1046C-3

Abstract: CY7C1046CV33 CY7C1046CV33-10VC CY7C1046CV33-10VI
Contextual Info: CY7C1046CV33 1M x 4 Static RAM Features • High speed — tAA = 10ns • Low active power for 10 ns speed — 324 mW max. • 2.0V data retention • Automatic power-down when deselected • TTL-compatible inputs and outputs • Easy memory expansion with CE and OE features

CY7C1046B

Abstract: CY7C1046B-12VC CY7C1046B-15VC CY7C1046B-20VC
Contextual Info: CY7C1046B CY7C1046B 1M x 4 Static RAM Features • High speed — tAA = 12 ns • Low active power — 935 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

CY7C1046D-10VXI

Abstract: V324 CY7C1046B CY7C1046D
Contextual Info: CY7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power

CY7C1046CV33

Abstract: CY7C1046DV33 CY7C1046DV33-10VXI
Contextual Info: CY7C1046DV33 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046CV33 • High speed — tAA = 10 ns • Low active power — ICC = 90 mA @ 10 ns • Low CMOS standby power — ISB2 = 10 mA • 2.0 V data retention

CY7C1046BV33

Abstract: CY7C1046BV33-10VC CY7C1046BV33-12VC CY7C1046BV33-15VC
Contextual Info: 046BV33 PRELIMINARY CY7C1046BV33 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power for 10 ns speed — 540 mW max. • Low CMOS standby power (L version) — 1.8 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

Contextual Info: CY7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description • Pin- and function-compatible with CY7C1046B The CY7C1046D is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is

CY7C1041BV33

Abstract: CY7C1046BV33 CY7C1049BV33
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 000305 VERSION 1.0 March, 2000 4 Meg Asynchronous SRAM R52D-3 Technology at Fab 4 CY7C1041BV33 256K x 16 Static RAM CY7C1046BV33 1M x 4 Static RAM CY7C1049BV33 512K x 8 Static RAM CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

Contextual Info: CY7C1046DV33 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features Functional Description • Pin- and function-compatible with CY7C1046CV33 The CY7C1046DV33 is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is

CY7C1046B-15VC

Abstract: CY7C1046B CY7C1046B-12VC
Contextual Info: ADVANCE INFORMATION CY7C1046B 1M x 4 Static RAM Features • High speed — tAA = 10 ns • Low active power — 1018 mW max. • Low CMOS standby power (L version) — 2.75 mW (max.) • 2.0V Data Retention (400 µW at 2.0V retention) • Automatic power-down when deselected

CY7C1046

Contextual Info: V CYPRESS ADVANCED INFORMATION CY7C1046 1M x 4 Static RAM Features sion is provided by an active LO W C hip Enable CE , an active LO W O utput Enable (O E), and th re e -sta te drivers. W riting to th e de vice is a c c o m plished by ta kin g C hip Enable (CE) and

V324

Abstract: CY7C1046B CY7C1046D CY7C1046D-10VXI
Contextual Info: CY7C1046D 4-Mbit 1M x 4 Static RAM Functional Description[1] Features • Pin- and function-compatible with CY7C1046B • High speed — tAA = 10 ns • CMOS for optimum speed/power • Low active power — ICC = 90 mA @ 10 ns • Low CMOS Standby Power

1046B-2

Abstract: 1046b8
Contextual Info: CY7C1046BN 1M x 4 Static RAM Features You write to the device by taking Chip Enable CE and Write Enable (WE) inputs LOW. Data on the four IO pins (IO0 through IO3) is then written into the location specified on the address pins (A0 through A19). • Low active power

Contextual Info: CY7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Functional Description Features The CY7C1046D is a high-performance CMOS static RAM organized as 1M words by 4 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW

Contextual Info: CY7C1046D 4-Mbit 1 M x 4 Static RAM 4-Mbit (1 M × 4) Static RAM Features provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and tri-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable