CY74FCT399TSOC Search Results

Contextual Info: fax id: 7022 CY74FCT399T CYPRESS Quad 2-Input Register Functional Description Features • Function, pinout and drive compatible with FCT and F logic • FCT-C speed at 6.1 ns max. FCT-A speed at 7.0 ns max. • Reduced V qh typically = 3.3V versions of equivalent

CY54FCT399CTLMB

Abstract: CY74FCT399ATPC CY74FCT399ATQC CY74FCT399CTPC CY74FCT399CTSOC
Contextual Info: CY54/74FCT399T CYPRESS Features Q uad 2-Input R egister • Function, pinout and drive compatible with FCT and F logic • FCT-C speed at 6.1 ns mux. Com'] FCT-A speed at 7.0 ns max. (Com’l) • Reduced Voh (typically = 3.3V) • ESD > 2000V • Fully compatible with TTL input and

Contextual Info: fax id: 7022 1CY 74FCT3 99T CY74FCT399T Quad 2-Input Register Features Functional Description • Function, pinout and drive compatible with FCT and F logic • FCT-C speed at 6.1 ns max. FCT-A speed at 7.0 ns max. • Reduced VOH typically = 3.3V versions of equivalent

54FCT399

Contextual Info: CY54/74FCT399T CYPRESS Features • Function, pinoul and drive compatible with FCT and F logic • FCT-C speed at 6.1 ns max. Com’l FCT-A speed at 7.0 ns max. (Com’I) • Reduced Y’o h (typically = 33V) versions of equivalent FCT functions • Edge-rate control circuitry for

CY54FCT399CTLMB

Abstract: CY74FCT399CTQC t45v
Contextual Info: CY54/74FCT399T CYPRESS Q u a d 2 - I n p u t R e g is te r Features • E S D > 2000V • Function, pinout and drive compatible with Ft’T and F logic • Fully compatible with TTL input and output logic levels • FCT-C speed at 6.1 ns max. Corn’ll FCT-A speed at 7.0 ns max. (Com’l

CY54FCT399CTLMB

Abstract: CY74FCT399CTPC CY74FCT399CTQC CY74FCT399CTSOC 54FCT399
Contextual Info: CY54/74FCT399T CYPRESS Quad 2-Input Register Features ♦ ESD > 2000V • Function, pin ou t an d drive com patible w ith FCT and F logic • • FCT-C speed a t 6,1 n s m ax. C om ’l FCT-A speed a t 7.0 n s m ax. (C om ’l) * S in k current • Source current

Contextual Info: CY54/74FCT399T Quad 2-Input Register V CYPRESS S . The selected data is transferred to a 4-bit output register synchronous with the LOW-to-HIGH transition of the Clock input (CP). The 4-bit D-type output register is fully edge-triggered. The Data inputs (I qx >I i x ) and Select input (S) must

CY54FCT399CTDMB

Abstract: CY54FCT399CTLMB CY74FCT399ATPC CY74FCT399CTPC CY74FCT399CTQC CY74FCT399CTSOC
Contextual Info: CY54/74FCT399T Quad 2ĆInput Register D D Features D Function, pinout and drive compatible D FCTĆC speed at 6.1 ns max. Com'l D toĆHIGH transition of the Clock input (CP). The 4Ćbit DĆtype output register is Sink current 64 mA (Com'l), Source current

CY74FCT399ATSOC

Abstract: CY74FCT399CT CY74FCT399CTSOC CY74FCT399T CY74FCT399TSOC
Contextual Info: fax id: 7022 —— — Æ jr r ~ 'f V D D CY74FCT399T 17 Q Q I 1 IT COO Quad 2-Input Register Features Functional Description • Function, pinout and drive compatible with FCT and F logic • FCT-C speed at 6.1 ns max. FCT-A speed at 7.0 ns max. • Reduced V qh typically = 3.3V versions of equivalent