CY37 Search Results

vp44

Abstract: CY37064 CY37064V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ v’*'» -^ jjÉBT * ¿f5 ’00“’'* '^ 7“T{• < 1; .r - - •■■■■■■ c PRELIMINARY CY37064V 3, £ ,.* k v / k J UltraLogic 3.3V 64-Macrocell ISR™CLPD — tPD = 8.5ns Features — ts = 5.0 ns • 64 macrocells in four logic blocks

CY37384

Abstract: CY37384V L0651
Contextual Info: = j— PRELIMINARY T. # CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout.

CY37384

Abstract: CY37384V
Contextual Info: PRELIMINARY CY37384 UltraLogic 384-Macrocell ISR™ CPLD — tS = 5.5 ns Features • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

Contextual Info: PRELIMINARY CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 n s • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6.5 ns Product-term clocking IEEE 1149.1 JTAG boundary scan Programmable slew rate control on individual l/Os

Contextual Info: ! ^ jjjjjy '•ttttttttWÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄW1- JM N K t t ♦ < ij / 5; PRELIMINARY *^ ' CY37384 UltraLogic 384-Macrocell ISR™ CPLD — ts = 5.5 ns Features — tco = 6 ns • 384 macrocells in 24 logic blocks • In-System Reprogrammable™ (ISR™

Contextual Info: ^ jjjjjy .•/$ $$$$I ♦ PRELIMINARY < ij /t t5;*^ ' CY37512 UltraLogic 512-Macrocell ISR™ CPLD — tco = 6 ns Features • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ (ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: PRELIMINARY Cr CY37192 UltraLogic 192-Macrocell ISR™ CPLD — tco = 4.5 ns Features • 192 macrocells in twelve logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

Contextual Info: Xgjf PRELIMINARY CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — ts = 7 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6.5 ns • • • • • • — JTAG-compliant on-board programming

CY37032V

Contextual Info: CY37032V PREUM INAm UltraLogic 32-Macrocell ISR™ CPLD — tPD = 8.5 ns Features — ts = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable™ ISR™ includes: — tco = 6.0 ns Product-term clocking IEEE 1149.1 JTAG boundary scan

Contextual Info: CY37192V UltraLogic 3.3V 192-Macrocell ISR™ CPLD Features — tpD = 12 ns — ts = 7 ns • 192 macrocells in twelve logic blocks • IEEE standard 3.3V operation — tco = 6 .5 ns • Product-term clocking — 3.3V ISR • IEEE 1149.1 JTAG boundary scan

CY37032V

Abstract: CY37032
Contextual Info: 56V Back PRELIMINARY CY37032V UltraLogicTM 32-Macrocell ISRTM CPLD — tPD = 8.5 ns Features — tS = 5.0 ns • 32 macrocells in two logic blocks • 3.3V In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • •

CY37512

Abstract: CY37512V
Contextual Info: Back PRELIMINARY CY37512V UltraLogic 3.3V 512-Macrocell ISR™ CPLD — tPD = 15 ns Features • 512 macrocells in 32 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes

CY37384

Abstract: CY37384V cpld internal
Contextual Info: Back PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Features — tPD = 15 ns — tS = 8 ns • 384 macrocells in 24 logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • •

lem lta 100p

Abstract: lem la 100-P CY37064
Contextual Info: CY37064 PR EU M IN Am UltraLogic 64-Macrocell ISR™ CPLD — ts = 4.0 ns Features — t co = 4.0 ns • 64 m a cro c ells in fo u r log ic blocks P ro d uct-term clo ckin g • In-S ystem R e p ro g ra m m ab le ™ IS R ™ JT A G -co m p liant o n-b oard p ro gram m in g

Contextual Info: CY37256V UltraLogic 3.3V 256-Macrocell ISR™ CPLD — tPD = 12 ns Features — tS = 7.0 ns • 256 macrocells in sixteen logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming • • • • • • • •

ultraISR CABLE

Abstract: CY37032P44-222JC 154J CY37032
Contextual Info: CY37032 PRELIMINARY UltraLogicTM 32-Macrocell ISRTM CPLD — tS = 3.0 ns Features • 32 macrocells in two logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming • • • • • • • • • • — Design changes don’t cause pinout changes

ultraISR CABLE

Contextual Info: PRELIMINARY CY37384V UltraLogic 3.3V 384-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features The CY37384V is designed with a robust routing architecture which allows utilization of the entire device with a fixed pinout. This makes Ultra37000 optimal for implementing on-board design changes using ISR without changing pinouts.

Contextual Info: CY37064V PRELIMINARY UltraLogic 3.3V 64-Macrocell ISR™ CPLD Features — tPD = 8.5 ns — tS = 5.0 ns • 64 macrocells in four logic blocks • 3.3V In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming — tCO = 6.0 ns Product-term clocking

Contextual Info: CY3600i FLASH370i ISR™ Programming Kit Features • Supports FLASH370i™ and Ultra37000™ devices for Ultra37000V 3.3V support, please see the Ultra37000 ISR™ Programming Kit data sheet, CY3700i • Jam programming language support for Ultra37000

CY37128

Abstract: 8361H JESD22 CY37128P84 tsmc mos 45
Contextual Info: Cypress Semiconductor Product Qualification Report QTP# 000607 VERSION 1.1 January, 2001 High-Performance CPLDs CY37128P84 Ultralogic 128-Macrocell ISR™ CPLDs CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA: Ed Russell Reliability Director 408 432–7069

tsmc mos 45

Abstract: CY37032 CY37032V tsmc eeprom 8361H CY37032VP Nitto-8000
Contextual Info: Cypress Semiconductor Qualification Report QTP# 99252 VERSION 1.0 September, 1999 High-Performance CPLDs CY37032P* UltraLogic 32-Macrocell ISR™ CPLDs 5V CY37032VP* UltraLogic™ 32-Macrocell ISR™ CPLDs (3V) CYPRESS TECHNICAL CONTACT FOR QUALIFICATION DATA:

S2112-05-ND

Abstract: cypress ultra37000 jtag FLASH370I 10-pin jtag
Contextual Info: 0i CY3600i FLASH370i ISR™ Programming Kit Features • Supports FLASH370i™ and Ultra37000™ devices for Ultra37000V 3.3V support, please see the Ultra37000 ISR™ Programming Kit data sheet, CY3700i • Jam programming language support for Ultra37000

CY37384

Abstract: tms 0119 256-pin Plastic BGA 17 x 17
Contextual Info: = m m m !Æ '^ r ^ r : c Q P R £ U M lm fíY CY37384 i í.-.-.-.í k v / k., UltraLogic 384-Macrocell ISR™ CPLD Features — ts = 5.5 ns — tc o = 6 ns • 384 m a cro c ells in 24 logic blo cks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

ic tlp 251

Abstract: tlp 071 o240 CY37512 CY37512V
Contextual Info: «oaHaoooiMMMWfMMMMMM!9:^ .-” ^ •■■■■■■ ^ 'S f c jjÉBT *¿f5’00“’’*<'^1; .r7“T{• PRELIMINARY CY37512V i k v/ k#> UltraLogic 3.3V 512-Macrocell ISR™ CPLD Fully Routable with 100% Logic Utilization Features — JTAG-compliant on-board programming