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CY28351 Datasheets (6)

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Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY28351		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	73.09KB	8
CY28351		Spectra Linear	Differential Clock Buffer/Driver	Original	PDF	145.32KB	7
CY28351OC		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	73.09KB	8
CY28351OC		Spectra Linear	Differential Clock Buffer/Driver	Original	PDF	145.34KB	7
CY28351OCT		Cypress Semiconductor	Differential Clock Buffer/Driver DDR400- and DDR333-Compliant	Original	PDF	73.09KB	8
CY28351OCT		Spectra Linear	Differential Clock Buffer/Driver	Original	PDF	145.33KB	7

CY28351 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
CY28351OC Contextual Info: CY28351-400 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60 – 273-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	cy28351-400 333-mhz 400-mhz 273-mhz +248-pin cy28351oc	PDF
CY28351 Abstract: CY28351OC CY28351OCT Contextual Info: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	cy28351 ddr400-ddr333-compliant 333-mhz +5400-mhz 200-mhz 48-pin cy28351oc cy28351oct	PDF
CY28351 Abstract: CY28351OC CY28351OCT Contextual Info: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	cy28351 333-mhz 400-mhz 200-mhz +348-pin cy28351oc cy28351oct	PDF
CY28351 Abstract: CY28351OC CY28351OCT 127-01-1 Contextual Info: CY28351 Differential Clock Buffer/Driver DDR400- and DDR333-Compliant Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications	Original	cy28351 ddr400-ddr333-compliant 333-mhz +6400-mhz 200-mhz 48-pin cy28351oc cy28351oct 127-01-1	PDF
Contextual Info: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the	Original	cy28351 48-pin	PDF
CY28351 Abstract: CY28351OC CY28351OCT Contextual Info: CY28351 Differential Clock Buffer/Driver Features Description • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs • External feedback pin (FBIN) is used to synchronize the	Original	cy28351 48-pin cy28351oc cy28351oct	PDF
Contextual Info: CY28351 Differential Clock Buffer/Driver Features Description • Supports 333-MHz and 400-MHz DDR SDRAM • 60- – 200-MHz operating frequency • Phase-locked loop PLL clock distribution for double data rate synchronous DRAM applications • Distributes one clock input to ten differential outputs	Original	cy28351 333-mhz 400-mhz 200-mhz +148-pin	PDF