CY14B104L Search Results

SRAM 54-PIN TSOP

Contextual Info: PRELIMINARY CY14B104L/CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns and 25 ns access times • Internally organized as 512K x 8 or 256K x 16 • Hands-off automatic STORE on power down with only a small capacitor • STORE to QuantumTrap nonvolatile elements is initiated

TSOP II 54

Abstract: TSOP 48 thermal resistance junction to case TSOP 48 thermal resistance TSOP 54 thermal resistance
Contextual Info: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small

CY14B104L

Abstract: CY14B104N
Contextual Info: Issues in Ganging HSB Pins on CY14B104L/CY14B104N AN50741 Author: Gaurav Singh Associated Project: No Associated Part Family: CY14xxxx Software Version: None Associated Application Notes: AN43380 Application Note Abstract This application note discusses potential issues that occur when ganging HSB pins of multiple CY14B104L and CY14B104N

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off Automatic STORE on power down with only a small

Contextual Info: CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands Off Automatic STORE on Power Down with only a Small

Contextual Info: PRELIMINARY CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands off automatic STORE on power down with only a small

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

CY14B104LA-ZSP25XI

Abstract: TSOP II 54
Contextual Info: PRELIMINARY CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands off Automatic STORE on power down with only a small

CY14B104NA

Contextual Info: CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands Off Automatic STORE on Power Down with only a Small

Contextual Info: PRELIMINARY CY14B104L, CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands Off Automatic STORE on Power Down with only a Small

Contextual Info: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small

TSOP 54 Package

Abstract: CY14B104L CY14B104N
Contextual Info: CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off Automatic STORE on power down with only a small

BAP 16 voltage regulator

Abstract: BAP 52
Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP II) ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS) compliant ■ 20 ns, 25 ns, and 45 ns access times

CY14B104L

Abstract: CY14B104N
Contextual Info: PRELIMINARY CY14B104L, CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small

Contextual Info: CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands Off Automatic STORE on Power Down with only a Small

Contextual Info: CY14B104LA, CY14B104NA 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 20 ns, 25 ns, and 45 ns Access Times ■ Internally Organized as 512K x 8 (CY14B104LA) or 256K x 16 (CY14B104NA) ■ Hands Off Automatic STORE on Power Down with only a Small

TSOP 54 PIN

Abstract: TSOP 54 Package CY14B104L CY14B104N
Contextual Info: PRELIMINARY CY14B104L, CY14B104N 4 Mbit 512K x 8/256K x 16 nvSRAM Features Functional Description • 15 ns, 20 ns, 25 ns, and 45 ns access times ■ Internally organized as 512K x 8 (CY14B104L) or 256K x 16 (CY14B104N) ■ Hands off automatic STORE on power down with only a small

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)

TSOP 54 Package

Abstract: TSOP 48 thermal resistance TSOP 54 PIN TSOP 54 Package used in where TSOP II 54 TSOP II 54 Package
Contextual Info: PRELIMINARY CY14B104L/CY14B104N 4-Mbit 512K x 8/256K x 16 nvSRAM Feature Functional Description • 15 ns, 25 ns, and 45 ns access times • Internally organized as 512K x 8 or 256K x 16 • Hands-off automatic STORE on power down with only a small capacitor

AN1064

Contextual Info: CY14B104LA, CY14B104NA 4-Mbit 512 K x 8/256 K × 16 nvSRAM 4-Mbit (512 K × 8/256 K × 16) nvSRAM Features • Packages ❐ 44-/54-pin thin small outline package (TSOP) Type II ❐ 48-ball fine-pitch ball grid array (FBGA) Pb-free and restriction of hazardous substances (RoHS)