CSIX Search Results

IP-CSIX-L1

Abstract: EP1S10F780C5 EP1S10F780C6 EP1S25F1020C6 EP20K400EFC672-1X
Contextual Info: Common Switch Interface CSIX-L1 MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 www.altera.com Core Version: 1.0.0 Document Version: 1.0.0 rev1 Document Date: November 2002 Copyright Common Switch Interface (CSIX-L1) MegaCore Function User Guide

mc 8040

Abstract: 809C ORSO82G5 PI40
Contextual Info: ispLever CORE TM CSIX-to-PI40 IP Core User’s Guide August 2003 ipug17_01 Lattice Semiconductor CSIX-to-PI40 IP Core User’s Guide Introduction Lattice’s CSIX-to-PI40 core provides a customizable solution allowing a CSIX interface to Agere Systems’ PI40

fbga -1932

Abstract: fb h35 EP4SGX180 EP4SE820 EP4S100G5
Contextual Info: 1. Overview for the Stratix IV Device Family September 2012 SIV51001-3.4 SIV51001-3.4 Altera Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor

Contextual Info: Thru-Hole Power Inductor ELECTRONICS INC. EPIXXXXXXAC5 & EPIXXXXXXAC5-LF • Optimized for National’s LM257X Series • Low loss material ensures operation in high frequency switching converters, such as Buck, Boost or as output averaging filter inductor

TZX 214 transistor

Abstract: EP1S60
Contextual Info: Section I. Stratix Device Family Data Sheet This section provides the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power

PRBS23

Abstract: SSTL-18 B DIN 5463 41v4 Altera fft megacore
Contextual Info: 6. DC & Switching Characteristics SGX51006-1.2 Operating Conditions Stratix GX devices are offered in both commercial and industrial grades. However, industrial-grade devices may have limited speed-grade availability. Tables 6–1 through 6–12 provide information on absolute maximum

transistor h5c

Abstract: TRANSISTOR SUBSTITUTION DATA BOOK 1993 HDTV transmitter receivers block diagram 1 phase pure sine wave inverter schematic intel 945 motherboard schematic diagram prbs pattern generator using analog verilog gx iec developer p1111 D84 TRANSISTOR soft ferrite handbook
Contextual Info: Stratix GX Device Handbook, Volume 2 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com SGX5V2-2.0 Copyright 2006 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

RL30A

Abstract: F1818 swn 357 EPI-F4040 ferrite ee25 D876 d8763 LM257X F2222 LM259X-L7
Contextual Info: E LE CT RON ICS I N C . Inductors w w w. p c a . c o m Contents Surface Mount Power Inductor Series PCA Part No. Inductance µH DCR (Ω Max.) IDC (A) Inductance L W H EPI-B20 Toroid Series 1.05 - 248 .011 - 2.225 .180 - 3.4 0.9 - 220 .330 .330 .270 EPI-B30 Toroid Series

CAN protocol basics

Abstract: TSOP RECEIVER CRC-16 and CRC-32 CRC-16 CRC-32 Serial RapidIO Infiniband Signal Path Designer
Contextual Info: White Paper SerialLite Protocol Overview Introduction SerialLite is a lightweight, point-to-point serial protocol suitable for both packet and streaming data applications. It has the advantages of low protocol overhead, low gate count, and minimal data transfer

APC 1500 UPS CIRCUIT DIAGRAM

Abstract: APC UPS 650 CIRCUIT DIAGRAM APC UPS CIRCUIT DIAGRAM schematic diagram apc UPS schematic diagram UPS 600 Power tree UPS APC CIRCUIT diagram schematic diagram UPS APC APC schematic diagram UPS 1500 APC "APC 1500" UPS CIRCUIT DIAGRAM UPS APC CIRCUIT
Contextual Info: HardCopy Series Handbook, Volume 1 Preliminary Information 101 Innovation Drive San Jose, CA 95134 www.altera.com H5V1-4.5 Copyright 2008 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

DIN 5463

Abstract: ep4sgx230f1517 floating point FAS coding using vhdl GPON block diagram verilog code for floating point adder EP4SGX70 F1517 aes 256 verilog code for 128 bit AES encryption
Contextual Info: Section I. Device Core This section provides a complete overview of all features relating to the Stratix IV device family, which is the most architecturally advanced, high-performance, low-power FPGA in the market place. This section includes the following chapters:

LVDS to mipi bridge

Abstract: RGB mipi bridge
Contextual Info: V A R - S O M - M X 6 S Y S T E M O N M O D U L E VA‘I“CITE LTD VA‘-“OM-MX F MX TM - “ D - -M V A R - S O M - M X 6 S Y S T E M O N M O D U L E VA R I SC I T E LT D VA‘-“OM-MX D 2012 Variscite Ltd. All Rights Reserved. No part of this document may be photocopied, reproduced, stored in a retrieval

Contextual Info: White Paper Traffic Management in Stratix GX Devices Introduction Data networks were designed to meet the rapidly increasing bandwidth requirements of Internet traffic, which increased line rates by 400 percent every 2 to 3 years. These initial networks were able to handle e-mail and web traffic, but were not able to make service providers a profit.

Q-64G

Abstract: C192 nas 624 base station controller
Contextual Info: PRS 64Gu Product Brief Packet Routing Switch PB PRS 64Gu / v0.5 / 12-19-2003 configurable fixed-size, fast packet switching and is capable of supporting either frame-based traffic through segmentation and reassembly or cell-based traffic. Protocol-independent, it enables

logic diagram to setup adder and subtractor

Abstract: AMPP biasing circuit circuit diagram of inverting adder CMOS Logic Family Specifications logic family specification programmable logic controller timers application EP1S60
Contextual Info: Stratix February 2002, ver. 1.0 Introduction Preliminary Information Features. Data Sheet The Stratix family of programmable logic devices PLDs is based on a 1.5-V, 0.13-µm, all-layer copper SRAM process, with densities up to 114,140 logic elements (LEs) and up to 10 Mbits of RAM. Stratix devices

TXC-04222AIOG

Contextual Info: EtherPHAST -48 Plus Device Highly Integrated OC-48/STM-16 Ethernet + SAN Mapper TXC-06742 TECHNICAL OVERVIEW PRODUCT PREVIEW LINE SIDE TERMINAL SIDE+1.8V +3.3V 4x1.25 GHZ 8B/10B Tx/Rx SerialSer. LineInterfaces Interfaces four 155.52 Mbit/s or one 622.08

Contextual Info: Stratix GX Overview Introduction Today’s high-speed applications need a reliable data transfer technology that gets information from source to destination fast. To meet this need, Altera introduces the Stratix GX device family, a powerful fusion of 3.125-Gbps transceiver technology with the industry’s fastest FPGA

Contextual Info: Freescale Semiconductor Data Sheet: Advance Information Document Number: IMX53AEC Rev. 4, 11/2011 MCIMX53xA i.MX53xA Automotive and Infotainment Applications Processors Package Information Plastic Package Case TEPBGA-2 19 x 19 mm, 0.8 mm pitch Ordering Information

sAMSUNG CK 5081 T MANUAL

Abstract: 64 bit carry-select adder verilog code intel 915 MOTHERBOARD pcb CIRCUIT diagram inverter PURE SINE WAVE schematic diagram mercury motherboards regulator ic intel 775 motherboard diagram TRANSISTOR SUBSTITUTION DATA BOOK 1993 AW 55 IC vhdl code for cordic matlab code using 8 point DFT butterfly
Contextual Info: Stratix Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 408 544-7000 http://www.altera.com S5V1-1.2 Copyright 2003 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other words and logos that are identified as trademarks and/or service marks are, unless noted otherwise, the trademarks and

10Gb CDR

Abstract: 10GMII UNITED TECHNOLOGIES MICROELECTRONICS CENTER ORT82G5 STS-48 FPSC 020NC
Contextual Info: Preliminary Product Brief January 2001 ORCA ORT82G5 1.25/2.5/3.125 Gbits/s Backplane Interface FPSC Introduction Lucent Technologies Microelectronics Group has developed a next generation FPSC intended for highspeed serial backplane data transmission. Built on

EPC16

Abstract: FA12 APEX 20ke development board sram pin assignments
Contextual Info: APEX II May 2001, ver. 1.1 Features. Data Sheet • Preliminary Information ■ ■ Altera Corporation A-DS-APEXII-1.1 Programmable Logic Device Family Programmable logic device PLD manufactured using a 0.15-µm alllayer copper-metal fabrication process (up to eight layers of metal)

vhdl code for All Digital PLL

Abstract: 4000 CMOS texas instruments
Contextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.4 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

S 566 b

Abstract: TIMER FINDER TYPE 85.32 4000 CMOS texas instruments 16 bit data bus using vhdl 433 mhz rf transmitter pcb layout GX600
Contextual Info: Stratix IV Device Handbook Volume 1 Stratix IV Device Handbook Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V1-4.5 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat.

write a program of adder or subtractor

Abstract: EP1S60 SSTL-18 serdes circuitry sdr sdram pcb layout
Contextual Info: Stratix New Levels of System Integration October 2002 New Levels of System Integration Introducing Stratix FPGAs, Altera’s newest product family that breaks the performance and density barriers for high-density programmable logic. The Stratix family is