CQ 207 Search Results

DIN22

Abstract: MN6617 yamaha ic ym3623
Contextual Info: m *•> V h *»\ \ rs < ¡z S o W C J O I ^ S ^ 5 g V ml cof 0 W_ pi >“ ^ s s s 0 0 1 m p 2 * E 'k K S 8 s — N rs O O W j ftj a B K g 8 O CQ _J CQ > ^ 8 8 8 ■—11—11—11—11—11—11—11—11—i u O 00 CL 2 B£ BK í +6 »K a 4H 4H p » fet g g

SM84PG-ACTEL

Abstract: A1240XL SM-10 SM68P-ACTEL SM160PQ-ACTEL SM132CQ-ACTEL A42MX36 1200XL SM176TQ-ACTEL A1010DXV
Contextual Info: Silicon Sculptor - Adapter Module Selector Guide Page 1 of 3 BACK Adapter Module Selector Guide Package Types: BG - Plastic Ball Grid Array CQ - Ceramic Quad Flat Pack PG - Ceramic Pin Grid Array PL - Plastic J-Leaded Chip Carrier Device Type A1010B A1010B

z131

Abstract: Z1314 893Q C140 CY7C130 CY7C131 CY7C140 CY7C141 TSGB
Contextual Info: CYPRESS SEMI CONDUCTOR bSE D • 258ThbE DDGT73M 5TB, «CYP CY7C130/CY7C131 CY7C140/CY7C141 PY ppT ?cq SEMICONDUCTOR Features Functional Description • 0.8-micron CMOS for optimum speed/power • Automatic power-down • 1TL compatible • Capable of withstanding greater than

2N6262

Abstract: 2N5878 2N1487 2N1488 2N1489 2N1490 2N1702 2N3771 2N3772 2N4347
Contextual Info: 2848352 DIODE T R A N S I S T O R CO INC ñ4 84D 00121 D T- 33- fS |5ñ4ñ352 0000151 ñ CQ.,ir\ic. 201 68¿0400 • Telex; 139-385 • Outside NY & NJ area call TOLL FREE 800-526-4581 FAX No. 201-575-5863 lc(MAX)2.0 to 50A • T ype* 1 PMP Comple­ m ent

2N4211

Abstract: 2N5872 2N1936 2N1937 2N3265 2N3266 2N3597 2N3598 2N3599 2N4210
Contextual Info: ”04 e-C g4Wæ~DlODE T R A M S ïS T O R C O DE |Efl4fl3S2 0 D 0 D 1 3 0 T INC 64 D 00 1 3 0 ~ D T-33-13 ~ D1QDE TRANSISTOR CQ.,1 \IC. (201 686-0400 • Telex: 139-385 • Outside NY & NJ area call TOLL FREE 800-526-4581 FAX No. 201-575-5863 NPNTO-63 PNP

AS8510

Contextual Info: AS8510 D a t a A cq u is i t io n D ev ic e f o r B a t t e r y S e n s o r s 1 General Description Option for multiplexing either one differential input, or two single The AS8510 is a virtually offset free, low noise, two channel measurement device. It is tailored to accurately measure battery

Contextual Info: AS8515 D a t a A cq u is i t io n S y st e m w i t h P o w e r M a n a g em en t and L IN Tr an sc e iv er for 12V Battery Sensor Applications 1 General Description The AS8515 is designed for simultaneous measurement of shunt current sensor signal and battery voltage by two independent ADC

DIODE 2N4002

Abstract: BD314 100-01A 2N5872 2N1936 2N1937 2N3265 2N3266 2N3597 2N3598
Contextual Info: ^4 CöT833~2^DTÖTTE T R A N S I S T O R .CO INCT DE | E f l M f l 3 Sa Ö4D IID0D13D 1 00130 D ^ T -3 3 -1 3 D1QDE TRANSISTOR CQ.1WC. (201 686-0400 • Telex: 139-385 • Outside N Y & NJ area call T O LL F R E E 800-526-4581 FA X No. 201-575-5863 N P N T O -6 3

3h32

Contextual Info: o DRAWING MACE IM FH IAO ANCLE P R O JE C T IO N THIS DRAWING I S UNPU8LIS H E D . g cawi&rr is ay AMP jn cq rp c jra te d > V-OC HOC RELEASED FOR PUBLICATION 23 a l l in t e r n a t io n a l k is h t s R e a a tv E a . §otsr BD REVISIONS 39 ZONE G E5CRIPT 2ON

A1280XL

Abstract: A32100DX A3265DX A40MX02 A40MX04 A42MX09 A42MX16 A42MX24 A42MX36 A1225XL
Contextual Info: Component Selector Guide Mixed Voltage FPGA Selector Guide These FPGAs operate in 5.0V-only, 3.3V-only, or mixed 5.0V/3.3V systems. Device Type Speed Option2 Temp.3 Range 44 Std, -1, -2, -3 68 Std, -1, -2, -3 100 Std, -1, -2, -3 Pkg1 No. Pins PL PL PQ User

3M Touch Systems

Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth

CY7C1570KV18

Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles: ■ 550 MHz clock for high bandwidth

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.0 cycles: ■ 450 MHz Clock for High Bandwidth

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.0 cycles: ■ 450 MHz Clock for High Bandwidth

CY7C1570KV18-550BZI

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 PRELIMINARY 72-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles:

CY7C1568KV18

Abstract: CY7C1570KV18 psoc 3M Touch Systems
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth

3M Touch Systems

Contextual Info:  CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 72-Mbit density (8M x 8, 8M × 9, 4M × 18, 2M × 36) With Read Cycle Latency of 2.0 cycles: ■

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency Features Configurations • 72 Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.0 cycles: ■ 450 MHz clock for high bandwidth

CY7C1568KV18

Abstract: CY7C1570KV18 78 ball fbga thermal resistance
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • 72 Mbit Density (8M x 8, 8M x 9, 4M x 18, 2M x 36) With Read Cycle Latency of 2.5 cycles: ■ 550 MHz Clock for High Bandwidth

3M Touch Systems

Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations n 72-Mbit density (8M x 8, 8M x 9, 4M x 18, 2M x 36)

3M Touch Systems

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

3M Touch Systems

Abstract: CY7C1570KV18
Contextual Info: CY7C1566KV18, CY7C1577KV18 CY7C1568KV18, CY7C1570KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)

3M Touch Systems

Contextual Info: CY7C1546KV18, CY7C1557KV18 CY7C1548KV18, CY7C1550KV18 72-Mbit DDR II+ SRAM 2-Word Burst Architecture 2.0 Cycle Read Latency 72-Mbit DDR II+ SRAM 2-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations • 72-Mbit density (8 M x 8, 8 M × 9, 4 M × 18, 2 M × 36)