CONTROLLER LTA 702 N Search Results

Contextual Info: XL110 Keeloq Code Hopping Decoder Preliminary Information PIN CONFIGURATION FEATURES • Unique Master Transmitter for Each System EIAJ Small O utline "RF" Packaga ■ Up to Five 5 Learnable Other Transmitters Per Decoder R Ë S ff[T 0 ■ Each Transmitter has a Unique Key

IC29150

Contextual Info: Application Note 9 Design Considerations for 5V to 3.3V Pass Regulators By Bob Wolbert General Description The rise of 3.3V logic and memory com ponents in personal com puter system s has created dem and for 3.3V power supplies. Several options exist for the com puter system

Contextual Info: CXD2403AR SONY Timing Generator for Color Liquid Crystal Panel Description The C X D 2403A R is a tinning signal g e n e ra to r for color liquid crystal panel drivers. Features • G e n e ra te s th e L C X 0 0 3 , L C X 0 0 4 and L C X 0 0 5 drive pulses

Diode in5819

Abstract: controller LTA 702 N TTI5870 CTX031 smps to motherboard wiring diagram POWER SUPPLY RPS 5467 MAX782
Contextual Info: 19-0146; Rev 1; 8/93 y k iy ix iy i/ i Triple-Output Pow er-Supply C ontroller for N otebook Com puters High efficiency 95% at 2A; greater than 80% at loads from 5mA to 3A is achieved through synchronous recti­ fication and PWM operation at heavy loads, and IdleModeTM operation at light loads. It uses physically

controller LTA 702 N

Contextual Info: 19-0221; Rev 0; 9/94 A 1 / X I A 1 - _. I k ,t WlftNVJM-S eVÄ 0 W 0 A T A S H e 5 L _ S te p -D o w n C o n tro lle rs w ith Synchronous R e c tifie r fo r C P U P o w e r _Features ♦ 96% Efficiency The MAX796/MAX799 are specially equipped with a sec­

dual tracking power supply

Abstract: CA3094T thermistor ntc 180m CA3094 0MA810 AN6048 transistor 2sc 1014 P-8609 CA3080 CA3094A
Contextual Info: M3DES71 H A OGSSTTD R R T33 • H AS I S C * A S E M I C O N D U C T O R M 'I f i Q d M Programmable Power Switch/Amplifier for Control and General Purpose Applications April 1994 Features Description • • • • • The CA3094 is a differential input power control switch/

I9100

Abstract: controller LTA 702 N
Contextual Info: Tem ic AN704 S e m i c o n d u c t o r s Designing DC/DC Converters to Meet CCITT Specifications for ISDN Terminals In te g ra te d S e rv ic e s D ig ital N e tw o rk IS D N sta n d a rd s a re a m a jo r s te p to w a rd s th e re a liz a tio n o f a w o rld w id e

controller LTA 702 N

Contextual Info: NWK914D MITEL PHY/PMD High Speed Copper Media Transceiver SEMICONDUCTOR Prelim inary Inform ation DS4829 - 1.1 The NW K914D is a P hysical Layer device designed for use in 100B A S E -T X a p p lic a tio n s . The N W K 914D has integrated the 100mb/s transceiver, clock and data recovery

Contextual Info: APRIL, 1996 LXT305 Integrated T1/E1 Short-Haul Transceiver withTransmit Jitter Attenuation General Description Features T he L X T305 is a fully integrated transceiver for both N orth A m erican 1.544 M bps T l and International 2.048 M bps ( E l) applications. T ransm it p ulse shapes (T l or E l) are

controller LTA 702 N

Abstract: BT812 bt812 equivalent
Contextual Info: VP520S M ITEL PAL/NTSC to CIF/QCIF Converter S E M IC O N D U C T O R Advance Information Supersedes version in June 1995 Digital Video & DSP IC Handbook, HB3923-2 DS3504 - 3.2 O ctober 1996 FEATURES DESCRIPTION • Lower Power, pin compatible replacement for VP520

intel 8039

Abstract: processor 8049 8039 8039 intel 8049 intel microprocessor pin diagram I8049 intel 8049 microcomputer intel 8049 XRL Series instruction set of 8048
Contextual Info: in t e i P R S U M O IN lM R f 18049/8039 HIGH PERFORMANCE SINGLE COMPONENT 8-BIT MICROCOMPUTER INDUSTRIAL *8049 Mask Programmable ROM *8039 External ROM or EPROM *6 MHz Operation 8-Bit CPU, ROM, RAM, I/O in Single Package Single 5V ± 10% Supply 2K x 8 ROM

Contextual Info: . 5 > Standard Product February, 1994 1 LXT305A Low Power Tl/El Integrated Short Haul Transceiver with Transmit Jitter Attenuation Genera* Description Features The LXT305A is a fully integrated transceiver for both North American 1.544 MHz Tl , and European 2.048 MHz

48V 3A SMPS circuit diagram

Abstract: fly back transformer monitor i630
Contextual Info: 1 9-0480; R e v 2 ; t J V \Æ X A J V \ Multi-Output, Low-Noise Power-Supply Controllers for Notebook Computers Up to 96% efficiency is achieved through synchronous rectification and Maxim’s proprietary Idle Mode control scheme. Efficiency is greater than 80% over a 1000:1

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ELECTRON DEVICE jU P D 7 5 2 3 8 4 BIT SINGLE-CHIP MICROCOMPUTER The /¿PD75238 is a single-chip microcom puter which contains a CPU capable of 1-, 4-, and 8-bit data processing, ROM, RAM, and I/O ports. In addition, it contains a fluorescent display tube FIP controller/

C331M

Contextual Info: Single Chip DSP Motor Controller ADMC331 ANALOG DEVICES TARGET APPLICATIONS Washing Machines, Refrigerator Compressors, Fans, Pumps, Industrial Variable Speed Drives Edge Resolution to 38.5 ns 198 Hz Minimum Switching Frequency Double/Single Duty Cycle Update Mode Control

RCA 1A15

Abstract: 1A15 RCA RCA 1C7 RCA 1A11 1C11
Contextual Info: FINAL COM'L:-7/10/12/15 IND:-10/12/15/20 M A C H 5-128 V A N A N A M D T I S C O M P A N Y MACH5-128/68-7/10/12/15 MACH5-128/104-7/10/12/15 MACH5-128/120-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS ♦ Fifth generation MACH architecture

DIODE d3s 57

Contextual Info: 19-0221; Rev 2: 4/96 JV W Y X A JV X Step-Down Controllers w ith Synchronous R e c tifie r for CPU P ow er Features ♦ 96% Efficiency The MAX796/MAX799 are specially equipped with a sec­ ondary feedback input SECFB for transformer-based dual-output applications. This secondary feedback path

32xe

Contextual Info: 28-Lead ROM-Based DSP Motor Controller ADMC328 ANALOG DEVICES Preliminary Technical Data TARGET APPLICATIONS Washing Machines, Refrigerator Compressors, Fans, Pumps, Industrial V ariable Speed Drives FEATURES 20 MIPS Fixed-Point DSP Core Single Cycle Instruction Execution 50 ns

Contextual Info: Order this data sheet by H4C/D MOTOROLA H SEMICONDUCTOR “ TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H P ER FO R M A NC E T R IP L E LAYER M ETAL S U B -M IC R O N CMOS ARRAYS The s u b -m ic ro n H 4C S e rie s ’ " CM OS gate array fa m ily and th e new

Transistor mcr 22-8 412

Contextual Info: O rd er U lis d a ta s h e e t b y H 4C /D MOTOROLA H4C SERIES SEMICONDUCTOR TECHNICAL DATA Advance Information H4C SERIES CMOS ARRAYS and the CDA™ ARCHITECTURE H IG H PER FO R M A N C E T R IP L E LAYER M ETA L The s u b -m ic ro n H 4 C S eries'“ CM O S gate array family and the new

CL 2181 ic

Abstract: AT/CL 2181 ic CL 2181
Contextual Info: ANALOG DEVICES DSP Microcomputers ADSP-2181 /ADSP-2183 FEATURES PERFORMANCE 30 ns Instruction Cycle Time @ 5.0 Volts 33 MIPS Sustained Performance 34.7 ns Instruction Cycle Time @ 3.3 Volts Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in

TMP87CC70

Contextual Info: TOSHIBA TMP87CC70/H70/K70A/M70A CMOS 8-Bit Microcontroller TMP87CC70F, TMP87CH70F, TMP87CK70AF, TMP87CM70AF The 87CC70/H70/K70A/M70A are the high speed and high performance 8-bit single chip microcomputers. These MCU contain 6-bit A/D conversion inputs and a VFT Vacuum Fluorescent Tube driver on a chip.

Vantis PRO PROGRAMMING SW

Abstract: HS 455 e
Contextual Info: MACH 5 Family Fifth Generation MACH Architecture V AN A IM A M D T I S C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ Fifth generation MACH architecture — 100% routable — Pin-out retention — Four p o w e r/sp ee d options per block for m axim um perform ance and low est pow er

an6311

Abstract: Widlar AN-1 LT 7210 zener diode LM373 lm170 10 amp HIGH VOLTAGE FAST-SWITCHING npn darlington lm741 LH0002N lm380 equivalent national an-2 switching regulator
Contextual Info: rABMMiirfiHMiarggsagg LINEAR H ? M g / 0 K]g KCA COMPONENTS, 8 WALLIS COUBT «•EXlNGTON, MASS, « 1 7 3 6 1 7 8 6 1 -9 0 2 4 National P R E F A C E The p u rp o se of th is h a n d b o o k is to p ro v id e a fu lly in d e xe d and c ro s s -re fe re n c e d c o lle c tio n of lin e a r in ­