Part Number
    Please enter a valid full or partial manufacturer part number with a minimum of 3 letters or numbers

    COMMUNICATION CONTROL VERILOG CODE Search Results

    COMMUNICATION CONTROL VERILOG CODE Result Highlights (5)

    Part ECAD Model Manufacturer Description Download Buy
    8251A/BXA
    		Rochester Electronics LLC 8251 - Programmable Communication Interface, NMOS, CDIP28 PDF Buy
    54LS190/BEA
    		Rochester Electronics LLC 54LS190 - BCD Counter, 4-Bit Synchronous Up/Down, With Mode Control - Dual marked (M38510/31513BEA) PDF Buy
    9519ADM/B
    		Rochester Electronics LLC 9519A - Universal Interrupt Controller PDF Buy
    D8274
    		Rochester Electronics LLC 8274 - Multi-Protocol Serial Controller (MPSC) PDF Buy
    MD82510/B
    		Rochester Electronics LLC 82510 - Serial I/O Controller, CMOS, CDIP28 PDF Buy

    COMMUNICATION CONTROL VERILOG CODE Datasheets Context Search

    Catalog Datasheet Type Document Tags PDF

    vhdl code for rs232 receiver

    Abstract: xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl
    Contextual Info: Application Note: CPLD R UARTs in Xilinx CPLDs XAPP341 v1.3 October 1, 2002 Summary This application note provides a functional description of VHDL and Verilog source code for a UART. The code is used to target the XC95144, XCR3128XL, or XC2C128 CPLDs. The


    Original     		XAPP341 XC95144, XCR3128XL, XC2C128 RS232. XAPP341 XCR3128 XCR3128XL vhdl code for rs232 receiver xilinx uart verilog code interface of rs232 to UART in VHDL vhdl code for uart communication vhdl code for serial transmitter vhdl code 16 bit microprocessor uart verilog code verilog code for serial transmitter verilog code for 8 bit shift register parallel to serial conversion vhdl PDF

    cyclic redundancy check verilog source

    Abstract: vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester code vhdl manchester verilog code for uart communication manchester manchester verilog decoder vhdl code for uart communication
    Contextual Info: Application Note: CoolRunner CPLDs R XAPP339 v1.3 October 1, 2002 Manchester Encoder-Decoder for Xilinx CPLDs Summary This application note provides a functional description of VHDL and Verilog source code for a Manchester Encoder Decoder. The reasons to use Manchester code are discussed. The code


    Original     		XAPP339 XC9572, XCR3064XL, XC2C64 XAPP339 cyclic redundancy check verilog source vhdl code manchester encoder vhdl code for manchester decoder vhdl code for clock and data recovery manchester code vhdl manchester verilog code for uart communication manchester manchester verilog decoder vhdl code for uart communication PDF

    AN070

    Abstract: philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070
    Contextual Info: INTEGRATED CIRCUITS AN070 Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs 1997 May 14 Philips Semiconductors Philips Semiconductors Application note Verilog implementation of a Manchester Encoder/Decoder in Philips CPLDs AN070 In this application note, Manchester code is defined, and the


    Original     		AN070 AN070 philips application manchester manchester code verilog manchester verilog decoder manchester encoder an070 PDF

    XILINX vhdl code REED SOLOMON

    Abstract: vhdl code REED SOLOMON XILINX vhdl code download REED SOLOMON XC4000 XC4000E x8 encoder vhdl code for parity generator
    Contextual Info: XF-RSENC Reed Solomon Encoder March 23, 1998 Product Specification AllianceCORE Facts Core Specifics1 Memec Design Services Maria Aguilar, Project Coordinator 1819 S. Dobson Rd., Suite 203 Mesa, AZ 85202 Phone: +1 888-360-9044 USA +1 602-491-4311 (outside the USA)


    Original     		60MHz XILINX vhdl code REED SOLOMON vhdl code REED SOLOMON XILINX vhdl code download REED SOLOMON XC4000 XC4000E x8 encoder vhdl code for parity generator PDF

    vhdl code for home automation

    Abstract: low power 8051 microcontroller verilog code R8051XCCUSB2 verilog code for ethernet communication edik 8051 microcontroller development board R8051XC-CUSB2 8051 tcp ip camera interface with 8051 microcontroller R8051XC
    Contextual Info: R8051XCCUSB2 USB High Speed Development Platform The R8051XC-CUSB2 is a fast 8-bit 8051 microcontroller integrated with a USB High Speed Function Controller which meets the 2.0 revision of the USB specification. Integrates CAST cores and adds software stack:


    Original     		R8051XCCUSB2 R8051XC-CUSB2 R8051XC USBFS-51 R8051XC R8051XC-F) vhdl code for home automation low power 8051 microcontroller verilog code R8051XCCUSB2 verilog code for ethernet communication edik 8051 microcontroller development board 8051 tcp ip camera interface with 8051 microcontroller PDF

    tsmc 0.18

    Abstract: verilog code for frame synchronization vhdl code for 8 bit register vhdl synchronous parallel bus tsmc Stream Machine verilog code for stream processor
    Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Core Configurable for support of master or slave functionality 8-bit host controller interface The LIN core is a communication controller that transmits and receives complete LIN


    Original     		PDF

    LIN VHDL source code

    Abstract: LIN Verilog source code vhdl synchronous parallel bus LIN source code verilog code for frame synchronization vhdl code 8 bit processor buffer register vhdl parallel interface vhdl
    Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Megafunction Configurable for support of master or slave functionality 8-bit host controller interface The LIN megafunction is a communication controller that transmits and receives complete LIN frames to perform serial communication according to the LIN Protocol


    Original     		PDF

    R8051XC

    Abstract: Keil uVision verilog code for implementation of bluetooth verilog code for 8051 c code for mouse interfacing 8051 edik vhdl code for home automation flash controller verilog code mouse interfacing 8051 vhdl code for watchdog timer
    Contextual Info: R8051XC-CUSB USB Full Speed Development Platform The R8051XC-CUSB is a fast 8-bit microcontroller integrated with a USB Full Speed Function Controller which meets the 1.1 revision of the USB specification. Integrates CAST cores and adds software stack: R8051XC 8-bit microcontroller


    Original     		R8051XC-CUSB R8051XC-CUSB R8051XC USBFS-51 Keil uVision verilog code for implementation of bluetooth verilog code for 8051 c code for mouse interfacing 8051 edik vhdl code for home automation flash controller verilog code mouse interfacing 8051 vhdl code for watchdog timer PDF

    XILINX vhdl code REED SOLOMON

    Abstract: vhdl code REED SOLOMON XILINX vhdl code download REED SOLOMON error correction code in vhdl encoder verilog coding vhdl code for dvb vhdl code download REED SOLOMON vhdl code for 9 bit parity generator error correction, verilog source verilog code for service description table table
    Contextual Info: XF-RSENC Reed Solomon Encoder November 9, 1998 Product Specification AllianceCORE Facts Core Specifics Memec Design Services Maria Aguilar, Project Coordinator 1819 S. Dobson Rd., Suite 203 Mesa, AZ 85202 Phone: +1 888-360-9044 USA +1 602-491-4311 (outside the USA)


    Original     		PDF

    verilog code for stream processor

    Abstract: LIN source code LIN ACTUATORS XC3S250E V200E LIN verilog source code verilog code for frame synchronization
    Contextual Info: Support of LIN specification 2.0 Programmable data rate between 1 Kbit/s and 20 Kbit/s LIN 8-byte data buffer Controller Core Configurable for support of master or slave functionality 8-bit host controller interface Slave can be implemented with or without clock synchronization


    Original     		PDF

    verilog code for 32 BIT ALU multiplication

    Abstract: 16 BIT ALU design with verilog code verilog code for 32 BIT ALU implementation 16 BIT ALU design with verilog hdl code 8 BIT ALU design with verilog code verilog code for ALU implementation verilog code for 32 BIT ALU division 8 BIT microprocessor design with verilog hdl code C68000 M6800
    Contextual Info: Control Unit o 16-bit two levels instruction decoder C68000 16-bit Microprocessor Core o Three levels instruction queue 55 instructions and 14 address modes Supervisor and User mode o Independent stack for both modes Users registers The C68000 is core of a powerful 16/32-bit microprocessor and is derived from the Motorola MC68000 microprocessor. The C68000 is a fully functional 32-bit internal and 16bit external equivalent for the MC68000. The C68000 serves interrupts and exceptions,


    Original     		16-bit C68000 C68000 16/32-bit MC68000 32-bit 16bit MC68000. verilog code for 32 BIT ALU multiplication 16 BIT ALU design with verilog code verilog code for 32 BIT ALU implementation 16 BIT ALU design with verilog hdl code 8 BIT ALU design with verilog code verilog code for ALU implementation verilog code for 32 BIT ALU division 8 BIT microprocessor design with verilog hdl code M6800 PDF

    xilinx uart verilog code

    Abstract: verilog code for uart communication verilog hdl code for uart design of UART by using verilog verilog code for digital modulation X345 Design and Simulation of UART Serial Communication XAPP341 pulse position modulation demodulation uart verilog code
    Contextual Info: Application Note: CoolRunner CPLD R IrDA and UART Design in a CoolRunner CPLD XAPP345 v1.3 December 23, 2003 Summary This application note illustrates the implementation of an IrDA and UART system using a CoolRunner CPLD. The fundamental building blocks required to create a half-duplex IrDA


    Original     		XAPP345 XC2C128 XCR3128XL XAPP341: QAN20. xilinx uart verilog code verilog code for uart communication verilog hdl code for uart design of UART by using verilog verilog code for digital modulation X345 Design and Simulation of UART Serial Communication XAPP341 pulse position modulation demodulation uart verilog code PDF

    verilog code for 16 bit ram

    Abstract: verilog code AMBA AHB amba ahb verilog code design 4 channels of dma controller AHB Slave using verilog verilog code for ahb bus slave utmi interrupt controller verilog code AMBA AHB
    Contextual Info: USBHS-DEV  Full compliance with the USB 2.0 specification  Control endpoint 0 — fixed 64 Bytes size  Configurable for up to 15 IN and 15 OUT endpoints High Speed USB Device Controller Core The USBHS-DEV core implements a complete high/full-speed 480/12 Mbps peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a


    Original     		LFE2M35E-7 verilog code for 16 bit ram verilog code AMBA AHB amba ahb verilog code design 4 channels of dma controller AHB Slave using verilog verilog code for ahb bus slave utmi interrupt controller verilog code AMBA AHB PDF

    amba ahb verilog code

    Abstract: verilog code for 16 bit ram 8 BIT microprocessor design with verilog hdl code verilog hdl code for programmable peripheral interface 32 bit cpu verilog testbench interrupt controller verilog code
    Contextual Info: Full compliance with the USB 2.0 specification USBHS-DEV High Speed USB Device Controller Core The USBHS-DEV core implements a complete high/full-speed 480/12 Mbps peripheral controller that interfaces to a UTMI USB port transceiver on one side and to a system’s


    Original     		PDF

    verilog code for baud rate generator

    Abstract: r8051xc2-b 80517 80C51 R8051XC2 intel 8051 microcontroller INSTRUCTION SET
    Contextual Info:  Fully compatible with the MCS 51 instruction set  Single clock per cycle and effi- R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Megafunction cient architecture for up to 12.1 times the performance of original 8051  Fewer machine cycles means


    Original     		R8051XC2 R8051XC2 verilog code for baud rate generator r8051xc2-b 80517 80C51 intel 8051 microcontroller INSTRUCTION SET PDF

    1 wire verilog code

    Abstract: BUS BAR specification DS2502-E48 1-wire vhdl AN119 APP119 DS2408 DS89C200
    Contextual Info: Maxim > App Notes > 1-Wire Devices ASICs Battery Management Keywords: DS1WM, 1WM, 1-Wire, 1-Wire Master, DS89C200, ASIC, Verilog, VHDL, 1wire, 1 wire Mar 08, 2002 APPLICATION NOTE 119 Embedding the 1-Wire® Master Abstract: This application note shows how to incorporate the 1-Wire Master 1WM into a user's ASIC design.


    Original     		DS89C200, DS89C200 fo492 com/an119 DS2408: DS2502-E48: AN119, APP119, Appnote119, 1 wire verilog code BUS BAR specification DS2502-E48 1-wire vhdl AN119 APP119 DS2408 PDF

    R8051XC2

    Abstract: verilog code for baud rate generator verilog code R8051XC2 r8051xc2-b 80515 80517 frequency counter using 8051 verilog code for slave SPI with FPGA verilog code 16 bit UP COUNTER verilog code for uart communication
    Contextual Info: Fully compatible with the MCS 51 instruction set R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Core The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set. The IP core runs with a single clock per machine cycle, and requires an average of 2.12


    Original     		R8051XC2 R8051XC2 verilog code for baud rate generator verilog code R8051XC2 r8051xc2-b 80515 80517 frequency counter using 8051 verilog code for slave SPI with FPGA verilog code 16 bit UP COUNTER verilog code for uart communication PDF

    intel 8051 Arithmetic and Logic Unit -ALU

    Abstract: Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 ASM51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051
    Contextual Info:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Megafunction An economical, entry-point, fixed-configuration megafunction that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as the 80C31, but executes operations an average of eight times faster.


    Original     		R8051XC-EP 8051-Compatible 8051-like ASM51 80C31, R8051XC-EP 80C51) intel 8051 Arithmetic and Logic Unit -ALU Memory Management 8051 8051 address decoder verilog code for ALU implementation 80C31 80C51 SAB80C537 verilog code for 32 BIT ALU implementation verilog code for 8051 PDF

    TMS380

    Abstract: XC4025 verilog code for communication between fpga verilog code
    Contextual Info: Cust omer - Au t hor ed Appl i cat i on N ot e HDL Methodology Offers Fast Design Cycle and Vendor Independence Joseph Cerra, Senior Design Engineer Wellfleet Communications Inc. In the highly competitive data communications field, the ability to bring a product to market quickly is essential for


    Original     		PDF

    verilog code for 8 BIT ALU implementation

    Abstract: verilog code for ALU implementation SAB80C537 8 BIT ALU design with verilog code 16 BIT ALU design with verilog code verilog code 16 bit UP COUNTER 16 BIT ALU design with verilog hdl code duty cycle program in 8051 verilog code for 32 BIT ALU implementation verilog code for 8051
    Contextual Info:  Control Unit − Eight-bit instruction decoder for MCS 51 instruction set R8051XC-EP 8051-Compatible Microcontroller Core An economical, entry-point, fixed-configuration core that implements an 8051-like 8-bit microcontroller that executes all ASM51 instructions. It has the same instruction set as


    Original     		R8051XC-EP 8051-Compatible 8051-like ASM51 80C31, R8051XC-EP verilog code for 8 BIT ALU implementation verilog code for ALU implementation SAB80C537 8 BIT ALU design with verilog code 16 BIT ALU design with verilog code verilog code 16 bit UP COUNTER 16 BIT ALU design with verilog hdl code duty cycle program in 8051 verilog code for 32 BIT ALU implementation verilog code for 8051 PDF

    16 BIT ALU design with verilog/vhdl code

    Abstract: 8 BIT ALU design with verilog/vhdl code 32 BIT ALU design with verilog/vhdl code ahb master bfm ARM7 pin diagram d00000-d00040 ARM7 instruction set cycle timing summary 32 BIT ALU design with verilog/vhdl advantages of arm7 ARM7
    Contextual Info: CoreMP7 Product Summary • • • • • • • Verification and Compliance • • Personal Audio MP3, WMA, and AAC Players Personal Digital Assistants Wireless Handset Pagers Digital Still Camera Inkjet/Bubble-Jet Printer Monitors Compliant with ARMv4T ISA


    Original     		PDF

    DOWN COUNTER using 8051

    Abstract: R8051XC2 verilog code for 32 BIT ALU multiplication verilog code R8051XC2 80C51 frequency counter using 8051 alarm clock 8051 microcontroller uart verilog MODEL r8051xc2-b R8051XC2-AF
    Contextual Info: Fully compatible with the MCS 51 instruction set R8051XC2 High-Performance, Configurable, 8-bit Microcontroller Core The R8051XC2 configurable processor core implements a range of fast, 8-bit, microcontrollers that execute the MCS®51 instruction set. The IP core runs with a single clock per machine cycle, and requires an average of 2.12


    Original     		R8051XC2 R8051XC2 80C51 R8051XC2-BF 80515/80517-like DOWN COUNTER using 8051 verilog code for 32 BIT ALU multiplication verilog code R8051XC2 frequency counter using 8051 alarm clock 8051 microcontroller uart verilog MODEL r8051xc2-b R8051XC2-AF PDF

    micron ddr3

    Abstract: DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC
    Contextual Info: Maxim > Design Support > App Notes > T/E Carrier and Packetized > APP 5120 Keywords: DDR1, DDR3, jitter, buffer, TDMoP, TDM over packet, DDR, SDRAM, PDV, PSN, double data rate APPLICATION NOTE 5120 Aug 26, 2011 Using a DDR3 Memory Module with the DS34S132


    Original     		DS34S132 DS34S132, 32-point DS34S132 256ms 32-port com/an5120 micron ddr3 DDR3 timing diagram DDR3 model verilog codes Verilog DDR3 memory model micron memory model for ddr3 MT41J128M8 Verilog DDR memory model DDR3 "application note" DDR3 DQ flip flop IC PDF

    verilog code for slave SPI with FPGA

    Abstract: EP1C3T100C8 vhdl spi interface vhdl spi bus VHDL code for slave SPI with FPGA "Serial peripheral interface" vhdl synchronous bus vhdl code for 8 bit shift register verilog code for 64 32 bit register
    Contextual Info: SPI_MS Serial Peripheral Interface Master/Slave Altera Core The Serial Peripheral Interface SPI allows high-speed synchronous serial data transfers between microprocessors, microcontrollers and peripheral devices. The SPI_MS core implements the Serial Peripheral Interface, which can operate either


    Original     		PDF