9s08dz60
Abstract: 3M05C 1M74K MC9S08DZ60 se110 AD10 HCS08 DZ60 MSCAN HCS08 an3776
Contextual Info: Freescale Semiconductor Application Note Document Number: AN3776 Rev. 0, 09/2008 MC9S08DZ60 Migrating from the 3M05C to M74K Mask Set by: D. Scott Brown Applications Engineering Microcontrollers Solutions Group Austin, TX, USA Gordon Borland Applications Engineering
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AN3776
MC9S08DZ60
3M05C
9S08DZ60
0M74K
1M74K
1M74K.
se110
AD10
HCS08
DZ60
MSCAN HCS08
an3776
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C288
Abstract: MPC555
Contextual Info: SECTION 7 RESET This section describes the MPC555 reset sources, operation, control, and status. 7.1 Reset Operation The MPC555 has several inputs to the reset logic which include the following: • Power on reset • External hard reset pin HRESET • External soft reset pin (SRESET)
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MPC555
MPC555
C288
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C288
Abstract: MPC555 MPC556 JTRS MPC555 "limp mode" watchdog
Contextual Info: SECTION 7 RESET This section describes the MPC555 / MPC556 reset sources, operation, control, and status. 7.1 Reset Operation The MPC555 / MPC556 has several inputs to the reset logic which include the following: • Power on reset • External hard reset pin HRESET
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MPC555
MPC556
0x0000
MPC556.
C288
JTRS
MPC555 "limp mode" watchdog
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CRC-16-CCITT
Abstract: 9S08Ac60 AN3494 CRC16-CCITT 9S08 AC60 HCS08 MC9S08AC60 MC9S08AW60 SBR12
Contextual Info: Freescale Semiconductor Application Note AN3494 Rev. 1, 04/2008 Migrating from the MC9S08AW60 to MC9S08AC60 by: Gordon Borland 8-Bit Applications Engineering Micro-Controller Division East Kilbride, Scotland 1 Introduction Freescale provides the MC9S08AC60 as a more flexible,
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AN3494
MC9S08AW60
MC9S08AC60
MC9S08AC60
MC9S08AW60.
HCS08
CRC-16-CCITT
9S08Ac60
AN3494
CRC16-CCITT
9S08
AC60
MC9S08AW60
SBR12
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mmu ericsson
Abstract: powerpc dhrystone POWERPC E500 POWERPC E500 instruction set coherency module Jumbo LED MPC8540 MPC190 MPC7450 MPC8260
Contextual Info: Motorola’s e500 Integrated Host Processor Dan Bouvier Motorola Semiconductor Products Sector Somerset Architecture Manager Microprocessor Forum 2001 MPC85xx Family Design Goals • Integration of RapidIO with a high performance, low power, 1 GHz e500 processor
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MPC85xx
256KB,
mmu ericsson
powerpc dhrystone
POWERPC E500
POWERPC E500 instruction set
coherency module
Jumbo LED
MPC8540
MPC190
MPC7450
MPC8260
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MPC566
Abstract: C288 MPC565
Contextual Info: SECTION 7 RESET This section describes the MPC565 / MPC566 reset sources, operation, control, and status. 7.1 Reset Operation The MPC565 / MPC566 has several inputs to the reset logic which include the following: • Power-on reset • External hard reset pin HRESET
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MPC565
MPC566
0x0000
MPC566.
MPC565/MPC566
C288
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"limp mode" motorola watchdog
Abstract: C288 MPC561 MPC563
Contextual Info: SECTION 7 RESET This section describes the MPC561 / MPC563 reset sources, operation, control, and status. 7.1 Reset Operation The MPC561 / MPC563 has several inputs to the reset logic which include the following: • Power-on reset • External hard reset pin HRESET
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MPC561
MPC563
MPC563.
MPC561/MPC563
"limp mode" motorola watchdog
C288
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marvell ethernet switch
Abstract: Marvell MIPS64
Contextual Info: RM9100 Released RM9100 Integrated Microprocessor FEATURES E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100 Integrated Processor is a high performance 64-bit MIPS -based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9100™
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RM9100
RM9100
E9000
RM9100TM
64-bit
RM9100TM
16-KByte,
256-KByte,
64-entry
PMC-2021479
marvell ethernet switch
Marvell
MIPS64
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MIPS64
Abstract: RM9220 "network interface cards"
Contextual Info: RM9220 Preliminary RM9220 Integrated Multiprocessor FEATURES The RM9220 Integrated Multiprocessor builds on the success of PMC-Sierra's next generation MIPS-based E9K processors by providing features specifically suited for network processing applications. It provides:
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RM9220
RM9220
MIPS64
16-Kbyte,
GPI-8/16/32
PMC-2021652
"network interface cards"
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FLOATING POINT Co Processor
Contextual Info: RM9100A Released PM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
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RM9100A
RM9100A
64-bit
RM9200A
E9000
MIPS64
16-KByte,
PMC-2040955
FLOATING POINT Co Processor
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Marvell
Abstract: MIPS64 RM9100A RM9200A
Contextual Info: RM9100A Released AM Integrated Microprocessor E9000 CORE CACHE AND I/O COHERENCY PMC-Sierra’s RM9100A Integrated Processor is a high performance 64-bit MIPS-based microprocessor with integrated memory and I/O interfaces. It is a single-core version of the RM9200A
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RM9100A
E9000
RM9100A
64-bit
RM9200A
16-KByte,
256-KByte,
64-entry
PMC-2040955
Marvell
MIPS64
RM9200A
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MIPS64
Abstract: RM9220
Contextual Info: RM9220 Released 54 4: :3 05 04 • Supports 25.6 Gbps memory. • Supports DDR SDRAM options. • Supports 2 Gbytes using 512 Mbit SDRAM and 4 Gbytes using 1 Gbit SDRAM. ADDITIONAL FEATURES • Provides 8 Kbytes integrated low latency scratch RAM. • Provides an integrated on-chip EJTAG
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RM9220
E9000
PMC-2021652
MIPS64
RM9220
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J1939
Abstract: J2284 MB14 MPC555 MPC556 749e
Contextual Info: SECTION 16 CAN 2.0B CONTROLLER MODULE The MPC555 / MPC556 contains two CAN 2.0B controller modules TouCAN . Each TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control systems. It is a high speed (1 Mbit/sec), short distance, priority based
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MPC555
MPC556
MPC556
J1939
J2284
MB14
749e
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J1939
Abstract: J2284 MB14 MPC555
Contextual Info: SECTION 16 CAN 2.0B CONTROLLER MODULE The MPC555 contains two CAN 2.0B controller modules TouCAN . Each TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial
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MPC555
MPC555
J1939
J2284
MB14
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MC68377
Abstract: FA80 J1939 J2284 MB14 basic stamp debug message
Contextual Info: SECTION 10 CAN 2.0B CONTROLLER MODULE TouCAN 10.1 Overview MC68377 contains one CAN 2.0B controller module (TouCAN™). The TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and industrial control
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MC68377
MC68377
FA80
J1939
J2284
MB14
basic stamp debug message
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78a4c
Abstract: J1939 J2284 MPC561 MPC563
Contextual Info: SECTION 16 CAN 2.0B CONTROLLER MODULE The MPC561 / MPC563 contains three CAN 2.0B controller modules TouCAN . Each TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and
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MPC561
MPC563
MIOS14
MPC561/MPC563
78a4c
J1939
J2284
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MPC566
Abstract: J1939 J2284 MB14 MPC565 78a4c J193 CMOS 7082
Contextual Info: SECTION 16 CAN 2.0B CONTROLLER MODULE The MPC565 / MPC566 contains three CAN 2.0B controller modules TouCAN . Each TouCAN is a communication controller that implements the controller area network (CAN) protocol, an asynchronous communications protocol used in automotive and
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MPC565
MPC566
MIOS14
MPC565/MPC566
J1939
J2284
MB14
78a4c
J193
CMOS 7082
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RM9122
Abstract: MIPS64
Contextual Info: RM9122 Preliminary FEATURES AM RM9122 Integrated Microprocessor NETWORKING INTERFACES • A CPU core compatible with the MIPS64 Instruction Set Architecture. • High-speed integrated DDR SDRAM, Local Bus, PCI, and Ethernet MAC interfaces. Option to bypass the
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RM9122
RM9122
MIPS64TM
672-pin
PMC-2031706
MIPS64
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MSC8156ADS Intrinsic Functions
Abstract: assembler 8156 neg_norm_l MSC8156ADS
Contextual Info: CodeWarrior Development Studio for StarCore DSP v10.1.3 Errata The table below lists the issues in this release along with a workaround for each. For more information on the resolution of any of these issues, please contact your customer support representative.
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MTWX40393
MTWX39721
MTWX40583
MTWX40569
MTWX40554
MTWX40470
MTWX40352
sc3000-ld
MTWX39931
MTWX39845
MSC8156ADS Intrinsic Functions
assembler 8156
neg_norm_l
MSC8156ADS
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MIPS64
Abstract: "network interface cards"
Contextual Info: RM9120 Preliminary FEATURES AM RM9120 Integrated Microprocessor NETWORKING INTERFACES • A CPU core compatible with the MIPS64 Instruction Set Architecture. • High-speed integrated DDR SDRAM, SysAD, Local Bus, HyperTransport, and Ethernet MAC interfaces. Option
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RM9120
MIPS64TM
672-pin
PMC-2031705
MIPS64
"network interface cards"
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mpc5510
Abstract: instruction set e200z0 MPC5500 SPR-62 ivor Lauterbach Datentechnik
Contextual Info: Freescale Semiconductor Application Note Document Number: AN3614 Rev. 0, 05/2008 Designing Code for the MPC5510 Z0 Core by: Daniel McKenna MCD Applications Engineering, EKB 1 Introduction One of the powerful features of the MPC5510 family of microcontrollers is its secondary Z0 core. This core, once
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AN3614
MPC5510
MPC5510
instruction set e200z0
MPC5500
SPR-62
ivor
Lauterbach Datentechnik
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API NETWORKS
Abstract: rm5200 sysad RM9000x2 Integrated Multiprocessor
Contextual Info: RM9000x2 Preliminary RM9000x2 Integrated Multiprocessor FEATURES DUAL CPU CORES CACHE AND I/O COHERENCY The RM9000x2™ Integrated Multiprocessor is PMC-Sierra's next generation high performance MIPS processor. The RM9000x2 follows in the footsteps of the very successful PMC-Sierra
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RM9000x2
RM9000x2
RM9000x2TM
RM7000TM
RM5200TM
MIPS64TM
RM9000,
RM7000,
API NETWORKS
rm5200
sysad
RM9000x2 Integrated Multiprocessor
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SE140
Abstract: se139 SE153 MCF51QE128 MCF51QE32 MCF51QE64 MCF51QE96 SE138-ICS 0M12J
Contextual Info: Freescale Semiconductor Mask Set Errata MSEF51QE128_0M12J Rev. 3, 5/2010 Mask Set Errata for Mask 0M12J Introduction This report applies to mask 0M12J for these products: • MCF51QE128 • MCF51QE96 • MCF51QE64 • MCF51QE32 SE184-FLVD-STOP3: False low voltage detect when exiting stop3
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MSEF51QE128
0M12J
0M12J
MCF51QE128
MCF51QE96
MCF51QE64
MCF51QE32
SE184-FLVD-STOP3:
SE140
se139
SE153
MCF51QE128
MCF51QE32
MCF51QE64
MCF51QE96
SE138-ICS
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RM7000
Abstract: API NETWORKS hypertransport Marvell MIPS64 RM5200
Contextual Info: RM9000x2 Preliminary AM RM9000x2 Integrated Multiprocessor DUAL CPU CORES CACHE AND I/O COHERENCY The RM9000x2™ Integrated Multiprocessor is PMC-Sierra's next generation high performance MIPS processor. The RM9000x2 follows in the footsteps of the very successful PMC-Sierra
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RM9000x2
RM9000x2
RM9000x2TM
RM7000TM
RM5200TM
16-Kbyte,
256-Kbyte,
Br8555
RM9000,
RM7000
API NETWORKS
hypertransport
Marvell
MIPS64
RM5200
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