CMOS TRISTATE BUFFER Search Results

AZP94

Contextual Info: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down

Contextual Info: VCC4 series 1.8, 2.5, 3.3, 5.0 volt CMOS Oscillator Features • CMOS output • Output frequencies to 125 MHz rd • Low jitter, Fundamental or 3 OT Crystal • Tristate output for board test and debug • -10/70 or –40/85°C operating temperature • Gold over nickel contact pads

IS41LV16105A

Contextual Info: ISSI IS41LV16105A 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE APRIL 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41LV16105A is 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page

IS41C16100

Abstract: 41C16100 IS41LV16100 60tl IS41C16100-50TLI
Contextual Info: IS41C16100 IS41LV16100 ISSI 1M x 16 16-MBIT DYNAMIC RAM WITH EDO PAGE MODE December 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories.

IS41LV16105

Contextual Info: ISSI IS41LV16105A 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE AUGUST 2004 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41LV16105A is 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page

IS41C16105

Abstract: IS41LV16105 IS41C16105-50TL N-40A
Contextual Info: IS41C16105 IS41LV16105 ISSI 1M x 16 16-MBIT DYNAMIC RAM WITH FAST PAGE MODE DECEMBER 2005 FEATURES DESCRIPTION • TTL compatible inputs and outputs; tristate I/O The ISSI IS41C16105 and IS41LV16105 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories. Fast Page Mode allows 1,024 random accesses within a single

circuit diagram of Tri-State Buffer using CMOS

Abstract: verilog code for UART with BIST capability block diagram for UART with BIST capability tri state AT28 vhdl code for flip-flop vhdl pid verilog code pid controller free vhdl code for usart
Contextual Info: Features • 0.5 µm Drawn Gate Length 0.45 µm Leff Sea-of-Gates Architecture with • • • • • Triple-level Metal Embedded E2 Memory up to 256 Kb 3.3V Operation with 5.0V Tolerant Input and Output Buffers High-speed, 200 ps Gate Delay, 2-input NAND, FO = 2 Nominal

atmel 424

Abstract: AMBIT inverter atmel 545 ATMEL 340 crystal oscillator buffer Structure of D flip-flop DFFSR s051 crystal OAI222 CMOS Transmission gate Specifications Tri-State Buffer CMOS
Contextual Info: Features • 0.5 µm Drawn Gate Length 0.45µm Leff Sea-of-Gates Architecture With Triple Level Metal • 3.3V Operation • 5.0V Compatible Input Buffers • On-chip Phase Locked Loop (PLL) Available to Synthesize Frequencies up to 150 MHz • • • •

MM80C96

Abstract: MM70C96 MM80C97 C1995 MM70C95 MM70C97 MM70C98 MM80C95 MM80C98 MM80C98N
Contextual Info: MM70C95 MM80C95 MM70C97 MM80C97 TRI-STATE Hex Buffers MM70C96 MM80C96 MM70C98 MM80C98 TRI-STATE Hex Inverters General Description Features These gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel enhancement mode transistors The MM70C95 MM80C95

MM74C941

Abstract: AN-90 C1995 J20A MM54C941 MM54C941J MM54C941N MM74C941J MM74C941N cmos octal buffers tri-state
Contextual Info: MM54C941 MM74C941 Octal Buffers Line Receivers Line Drivers with TRI-STATE Outputs General Description Features These octal buffers and line drivers are monolithic complementary MOS CMOS integrated circuits with TRI-STATE outputs These outputs have been specially designed to

MM80C96

Abstract: mm80c98 MM70C96
Contextual Info: MM70C95/MM80C95, MM70C97/MM80C97 TRI-STATE Hex Buffers MM70C96/MM80C96, MM70C98/MM80C98 TRI-STATE Hex Inverters General Description Features These gates are monolithic complementary MOS CMOS integrated circuits constructed with N- and P-channel en­ hancement mode transistors. The MM70C95/MM80C95

Contextual Info: a t i o n a l S e m i c o n d u c t o r MM54C941/MM74C941 Octal Buffers/Line Receivers/ Line Drivers with TRI-STATE Outputs General Description Features These octal buffers and line drivers are monolithic comple­ mentary MOS CMOS integrated circuits with TRI-STATE

Silego Technology

Abstract: NC7WZ126 74AUP2G126 74LVC2G126 NL27WZ126 SN74AUC2G126 SN74AUP2G126 SN74LVC2G126 marking NX texas datecode
Contextual Info: SLG74LB2G126 GreenLIBTM DUAL BUS BUFFER GATE WITH TRI-STATE OUTPUTS General Description Features The GreenLIB provides the dual bus buffer gate with tri-state • Pb-Free / RoHS Compliant outputs. The tri-state outputs are controlled by the output • Halogen-Free

Contextual Info: Çj Q r J I ST SINGLE TONE MELODY C-MOS WITH FEATURES BUFFER KJU5 1 1 DXX N J U S 1 1 CXI KJU5UM II P IN CONFIGURATION PAD LOCATION £ 1 V ss[ 2 14 [] Voo 13 ] n c 12 > c 11 H t c l 10 3 OUT 9 ]O U T 8 ]V ss tsm P .[ 3 P2[ 4 ncQ 5 6 NC n 7 endQ COORDINATES

74HC buffer tri-state output

Abstract: 74HC C1995 HC242 MM54HC242 MM54HC243 MM74HC MM74HC242 MM74HC243
Contextual Info: MM54HC242 MM74HC242 Inverting Quad TRI-STATE Transceiver MM54HC243 MM74HC243 Quad TRI-STATE Transceiver General Description These TRI-STATE bidirectional inverting and non-inverting buffers utilize advanced silicon-gate CMOS technology and are intended for two-way asynchronous communication between data buses They have high drive current outputs

Contextual Info: 54LCX245 Low Voltage Bidirectional Transceiver with 5V Tolerant Inputs and Outputs General Description Features The LCX245 contains eight non-inverting bidirectional buffers with TRI-STATE outputs and is intended for bus oriented applications. The device is designed for low voltage

rf amplifier marking catalog

Abstract: XC2301 tristate buffer cmos sot26 marking
Contextual Info: XC2301 Series ETR1409_001 Tri-State Buffer ICs •GENERAL DESCRIPTION The 2301 series are a group of high frequency, CMOS low power tri-state buffer ICs with input amplifier, divider and output tri-state buffer circuits built-in. Output can be selected from any one of the following values for fin input frequency : fin/1, fin/2, fin/4, fin/8.

XC2301

Abstract: Tri-State Buffer IC
Contextual Info: XC2301 Series ETR1409_001a Tri-State Buffer ICs •GENERAL DESCRIPTION The 2301 series are a group of high frequency, CMOS low power tri-state buffer ICs with input amplifier, divider and output tri-state buffer circuits built-in. Output can be selected from any one of the following values for fin input frequency : fin/1, fin/2, fin/4, fin/8.

VHCT244

Abstract: 74HC buffer tri-state output 74VHC244 74VHC244M 74VHC244MSC 74VHC244MTC 74VHC244SJ 74VHCT244 M20D
Contextual Info: 9 io .et N a t i o n a l S e m i c o n d u c t o r 74VHC244 • 74VHCT244 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’V H C /’VHCT244 is an advanced high speed CMOS oc­ tal bus buffer fabricated with silicon gate C2MOS technolo­

XC2300

Abstract: Tri-State Buffer CMOS
Contextual Info: XC2300 Series ETR1406_001a Tri-State Buffer ICs •GENERAL DESCRIPTION The 2300 Series are a group of high frequency, CMOS low power tri-state buffer ICs with input amplifier, divider and output tri-state buffer circuits built-in. The series is available in an ultra small SOT-26 package.

lcx125

Abstract: MA05B NC7LCX125M5 NC7LCX125M5X
Contextual Info: NC7LCX125 ß National Semiconductor NC7LCX125 Low-Voltage Single Buffer with 5V Tolerant Inputs and Outputs General Description Features The LCX125 contains a single non-inverting buffer with a TRI-STATE output. The inputs tolerate voltages up to 7V allowing the interface of 5V systems to 3V systems.

CH9083

Contextual Info: CH9083 Preliminary CHRONTEL DVD MPEG2 Clock Generator Features Description • Triple PLL output with buffered input reference frequency. • Single 27 MHz crystal supports all frequency requirements for MPEG2 playback. • Tristate buffered outputs with output enable

CERPAK

Contextual Info: 54FCT240 Octal Buffer/Line Driver with TRI-STATE Outputs General Description Features The 54FCT240 is an octal buffer and line driver designed to be employed as a memory address driver, clock driver and bus oriented transmitter or receiver which provides improved

Tri-State Buffer CMOS

Abstract: NJU6342 NJU6342H NJU6342XC NJU6342XE 780Q
Contextual Info: N J TR I-STATE Series PACKAGE OUTLINE O NJU6342XC NJU6342XE PIN CONFIGURATION/PAD LOCATION 4.0~6.0V 120MHz equivalent 2 1 8 □ □ □ CONT C x t 1 C 2 8 □ V| D 7 unc + D □ 3 4 a 5 NCC 3 6 D V "C 5 D F o. t CHIP/EMP 8 LINE-UP TABLE VERSION 2 BUFFER GENERAL DESCRIPTION