CMOS THRESHOLD VCC Search Results

Contextual Info: MM74HCT04 Hex Inverter Features General Description • TTL, LS pin-out and threshold compatible The MM74HCT04 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS—low quiescent power

Contextual Info: MM74HCT08 Quad 2-Input AND Gate Features General Description • TTL, LS pin-out and threshold compatible The MM74HCT08 is a logic function fabricated by using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS—low quiescent power

BY127

Contextual Info: 67C4500-35/50/65/80 a Deep First-in First-out FIFO 256x9 CMOS Memory O) » 01 DISTINCTIVE CHARACTERISTICS Retransmit capability Expandable in both width and depth Increased noise immunity for XI - CMOS threshold Functional and pin compatible with industry

Contextual Info: MM74HCT32 Quad 2-Input OR Gate Features General Description • TTL, LS pin-out and threshold compatible The MM74HCT32 is a logic function fabricated by using advanced silicon-gate CMOS technology, which provides the inherent benefits of CMOS—low quiescent

Contextual Info: MM74HCT00 Quad 2 Input NAND Gate Features General Description • TTL, LS pin-out and threshold compatible The MM74HCT00 is a NAND gates fabricated using advanced silicon-gate CMOS technology which provides the inherent benefits of CMOS—low quiescent power

BY127

Contextual Info: 67C4500-35/50/65/80 a Deep First-in First-out FIFO 256x9 CMOS Memory CT> -g O cn DISTINCTIVE CHARACTERISTICS Retransmit capability Expandable in both width andjieptfi Increased noise immunity for XI - CMOS threshold Functional and pin compatible with industry

Contextual Info: 67C4500-35/50/65/80 a Deep First-in First-out FIFO 256x9 CMOS Memory DISTINCTIVE CHARACTERISTICS Retransmit capability Expandable In both width an djiepth Increased noise immunity for XI - CMOS threshold RAM based FIFO 256x9 organization Cycle times of 45/65/80/100 nanoseconds

KS556

Contextual Info: SAMSUNG ELE CTRONICS INC 42E D KS556 H 7^4142 OOGSBlö^ T • SMGK CMOS INTEGRATED CIRCUIT CMOS DUAL TIMER The KS556 is a m onolithic Integrated circuit fabricated using CMOS process. Due to high Impedance Inputs Trigger, Threshold, Reset , It is capable o f producing accurate tim e delay using a less expensive,

JESD97

Abstract: VN808CM-E VN808CMTR-E
Contextual Info: VN808CM-E Low threshold octal high side driver General features Type RDS on Iout VCC VN808CM-E 160mΩ 0.7A 45V • CMOS compatible input ■ Junction over-temperature protection ■ Case over-temperature protection for thermal independence of the channels

Contextual Info: UNISONIC TECHNOLOGIES CO., LTD U74AHCT14 CMOS IC HEX SCHMITT-TRIGGER INVERTER „ DESCRIPTION The U74AHCT14 is a high speed Si-gate CMOS device which contains six independent Schmitt-trigger inverters and they perform the function Y=A. The device have different input threshold levels for positive-going

Contextual Info: 67C4502-35/50/65/80 a Deep First-in First-out FIFO 1024x9 CMOS Memory Oi O cn to 1 DISTINCTIVE CHARACTERISTICS w U) Dì Retransmit capability Expandable in both width and depth Increased noise immunity for XI - CMOS threshold RAM based FIFO 1024x9 organization

Contextual Info: VN808CM-E LOW THRESHOLD OCTAL HIGH SIDE DRIVER General Features Type RDS on Iout VCC VN808CM-E 160mΩ 0.7A 45V PowerSO-36 • CMOS COMPATIBLE INPUT ■ JUNCTION OVER-TEMPERATURE PROTECTION ■ CASE OVER-TEMPERATURE PROTECTION FOR THERMAL INDEPENDENCE OF THE

PS 1025

Contextual Info: AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable www.azmicrotek.com FEATURES DESCRIPTION • Minimizes External Components • Selectable Enable Polarity and Threshold CMOS or PECL • High Bandwidth for ≥1GHz • Similar Operation as

AZ100LVEL16VR

Contextual Info: AZ100LVEL16VR PECL/ECL Oscillator Gain Stage & Buffer with Selectable Enable www.azmicrotek.com FEATURES DESCRIPTION • Minimizes External Components • Selectable Enable Polarity and Threshold CMOS or PECL • High Bandwidth for ≥1GHz • Similar operation as

CMOS NE555

Contextual Info: S A M S U N G S E M I C O N D U C T O R INC “Jfl DE | 7 clti4145 0DD4ñt,7 7 T - S h t KS555H CMOS INTEGRATED CIRCUIT CMOS TIMER The KS555H is monolithic integrated circuit fabricated using CMOS process. Due to its high impedance inputs threshold, trigger, reset , it is capable of

AZP94

Contextual Info: AZP94 PECL/ECL ÷1, ÷2 Clock Generation Chip with Tristate Compatible Outputs www.azmicrotek.com FEATURES DESCRIPTION • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • Tristate Compatible Outputs • Input Buffer Powers Down

1026 soic-8

Abstract: CAT1021 CAT1022 CAT1023 CAT1024 CAT1025 CAT1026 CAT1027 CAT1161 CAT1162
Contextual Info: H CAT1026, CAT1027 Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM LE FEATURES • Precision VCC power supply voltage monitor ■ 16-Byte page write buffer — Five threshold voltage options ■ Built-in inadvertent write protection — Externally adjustable down to 1.25 V

Contextual Info: Advanced CAT24C163 16K , CAT24C083(8K) CAT24C043(4K), CAT24C023(2K) Supervisory Circuits with I2C Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer FEATURES • Active High or Low Reset Outputs ■ Watchdog Timer Input (WDI) ■ Programmable Reset Threshold

AZP92

Contextual Info: AZP92 PECL/ECL ÷1, ÷2 Clock Generation Chip with Selectable Enable www.azmicrotek.com FEATURES DESCRIPTION • 3.0V to 5.5V Operation • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • High Bandwidth o 1.5+ GHz (÷1)

Contextual Info: H CAT1026, CAT1027 Dual Voltage Supervisory Circuits with I2C Serial 2k-bit CMOS EEPROM LE FEATURES • Precision VCC power supply voltage monitor ■ 16-Byte page write buffer — Five threshold voltage options ■ Built-in inadvertent write protection — Externally adjustable down to 1.25 V

AZP92NA

Contextual Info: AZP92 PECL/ECL ÷1, ÷2 Clock Generation Chip with Selectable Enable www.azmicrotek.com FEATURES DESCRIPTION • 3.0V to 5.5V Operation • Selectable Divide Ratio • Selectable Enable Polarity and Threshold CMOS or PECL • High Bandwidth o 1.5+ GHz (÷1)

MM74C14J

Abstract: MM74C14N AN-90 C1995 J14A MM54C14 MM54C14J MM54C14N MM74C14 2474c
Contextual Info: MM54C14 MM74C14 Hex Schmitt Trigger General Description Features The MM54C14 MM74C14 Hex Schmitt Trigger is a monolithic complementary MOS CMOS integrated circuit constructed with N- and P-channel enhancement transistors The positive and negative going threshold voltages VT a

Contextual Info: a Advanced Micro Devices Am2064/Am2018 Programmable Gate Array DISTINCTIVE CHARACTERISTICS • Up to 1800 usable gate equivalence for higher board densities • Reconfigurable device for multiple in-system patterns • TTL or CMOS input threshold levels allow for more

PHILIPS DMOS FET

Contextual Info: Philips Components Data sheet status Preliminary specification BSS138 date of issue September 1990 N-channel enhancem ent m ode vertical D-M O S FET FEATURES PIN CONFIGURATION • Low threshold voltage • CMOS compatible • Low on-resistance. PINNING - SOT223