CMOS DUAL 64-STAGE STATIC SHIFT REGISTER Search Results

Q32A

Abstract: CD4517BMS Q32B
Contextual Info: CD4517BMS CMOS Dual 64-Stage Static Shift Register December 1992 Features Description • High-Voltage Types 20-Volt Rating CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following

CMOS Dual 64-Stage Static Shift Register

Abstract: CD4517BMS Q32A Q32B
Contextual Info: CD4517BMS CMOS Dual 64-Stage Static Shift Register December 1992 Features Description • High-Voltage Types 20-Volt Rating CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following

Q32A

Abstract: Q32B CD4517BMS
Contextual Info: CD4517BMS S E M I C O N D U C T O R CMOS Dual 64-Stage Static Shift Register December 1992 Features Description • High-Voltage Types 20-Volt Rating CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable

delta UPS circuit diagram

Contextual Info: CD4517BMS H A R R IS S E M I C O N D U C T O R CMOS Dual 64-Stage Static Shift Register D ecem ber 1992 Features Description • High-Voltage Types 20-Volt Rating CD4517BM S dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable

CD45178

Abstract: D4517
Contextual Info: 4 ^ 1 "j ß CD4517B Types CMOS Dual 64-Stage Static Shift Register The RCA-CD4517B dual 64-stage static sh ift register consists o f tw o independent registers each having a clo ck, data, and w rite enable in p u t and o utp uts accessible at taps fo llo w in g

Contextual Info: HARRIS SEMICOND SECTOR £ [} H A R R 44 E D I IS 4302271 Sflb 0037 C D 4 5 1 7 B S 3 HAS ^ T y p e s CMOS Dual 64-Stage Static Shift Register Q I6 &-Q 48 a -wea 16 —-voo z 15 — Qi 6 q 14 — 0408 13 -WEb 12 -CLg II — 0 6 4 a -

Contextual Info: T ex as In str u m e n t s CD4517B Types Data sheet acquired from Harris Sem iconductor S C H S075 CMOS Dual 64-Stage Static Shift Register Q I6 4 - I I 6 — VED 0 4 6 4 - 2 I 5 -Q|6 6 3 14 -0 4 8 0 4 13 — w eb CL6 Features: • Low quiescent current - 10 nA/pkg typ.

Contextual Info: CD4517B Types CMOS Dual 64-Stage Static Shift Register Q I 6 A - I Q 4 8 a - 2 T h e C D 4 5 1 7 B is supplied in 16-lead herm etic d u a l-in -lin e c e ra m ic p ac kag es D and F su ffixe s , 1 6 -le a d d u a l-in -lin e plastic p ac k­

mc1413 darlington pair

Abstract: MC1413 mc14094b MC14569 MC14024B MC14555B
Contextual Info: Table of Contents Page Page Numeric Data Sheet Listing Chapter 2: Data Sheets Numeric Data Sheet Listing . . . . . . . . . . . . . . . . . . . . . . . . . 4 Data Sheets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Chapter 1: Selector Guide

mc14569

Abstract: mc14094b MC14024B MC14555B
Contextual Info: CMOS Selection Guide by Function Device NAND Gates MC14011B MC14011UB MC14093B MC14023B Function Page Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Quad 2−Input NAND Gate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

hc4015

Contextual Info: [ /Title CD74 HC401 5 /Subject (High Speed CMOS Logic Dual 4- CD54/74HC4015 Data sheet acquired from Harris Semiconductor SCHS198A High Speed CMOS Logic Dual 4-Stage Static Shift Register November 1997 - Revised May 2000 Features Description • Maximum Frequency, Typically 60MHz

Q32B

Abstract: Q32A 4000B 4517B SCL4517B
Contextual Info: 4517B INTERNATIONAL, INC. CMOS 64-BIT DUAL SHIFT REGISTER FEATURES • Independent Clock, Write Enable Inputs • Static Operation • Positive Edge-Clocked Design • 6.7MHz Toggle Rate @ 10 VDC • Tri-State Output at 64th Bit • Balanced Output Drive Current Specifications

Contextual Info: R&E 4517B INTERNATIONAL, INC CMOS 64-BIT DUAL SHIFT REGISTER FEATURES • Independent Clock, W rite Enable Inputs • Static Operation • Positive Edge-Clocked Design • 6.7MHz Toggle Rate @ 10 VD C • Tri-State Output at 64th Bit • Balanced Output Drive Current Specifications

q32b

Abstract: Q32A DIODE MOTOROLA Case 403 MC14517B MC14XXXBCL MC14XXXBCP MC14XXXBDW
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14517B Dual 64-Bit Static Shift Register The MC14517B dual 64–bit static shift register consists of two identical, independent, 64–bit registers. Each register has separate clock and write enable inputs, as well as outputs at bits 16, 32, 48, and 64. Data at the data

HCF4517B

Abstract: HCF4517BEY HCF4517BM1 HCF4517M013TR
Contextual Info: HCF4517B DUAL 64 STAGE STATIC SHIFT REGISTER • ■ ■ ■ ■ ■ ■ ■ ■ CLOCK FREQUENCY 12MHz Typ. at VDD = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE STATE OUTPUTS QUIESCENT CURRENT SPECIFIED UP TO

HCF4517B

Abstract: HCF4517BEY HCF4517BM1 HCF4517M013TR HCF4517BE
Contextual Info: HCF4517B DUAL 64 STAGE STATIC SHIFT REGISTER • ■ ■ ■ ■ ■ ■ ■ ■ CLOCK FREQUENCY 12MHz Typ. at VDD = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOWS OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE STATE OUTPUTS QUIESCENT CURRENT SPECIFIED UP TO

HCC4517B

Abstract: HCC4517BF HCF4517B HCF4517BC1 HCF4517BM1
Contextual Info: HCC/HCF4517B DUAL 64-STAGE STATIC SHIFT REGISTER . . . . . . CLOCK FREQUENCY 12MHz TYP. AT VDD = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOW OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE-STATE OUTPUTS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE

Q32B

Contextual Info: £ÿj SGS-THOMSON l» om gT[RMÛÛS HCC/HCF4517B DUAL 64-STAGE STATIC SHIFT REGISTER CLOCK FREQUENCY 12MHz (TYP. AT Vdd = 10V SCHMITT TRIGGER CLOCK INPUTS ALLOW OPERATION WITH VERY SLOW CLOCK RISE AND FALL TIMES THREE-STATE OUTPUTS QUIESCENT CURRENT SPECIFIED AT 20V

4001UB

Abstract: 4737V 4059b 4086B HE4000B 40244B 4000UB 4521B 4541B
Contextual Info: FUNCTIONAL yv IN D E X CMOS HE4000B F A M ILY SURVEY Type numbers have a suffix which signifies the type of package and burn-in option: P = plastic Dl L; D = ceramic cerdip Dl L; T = plastic SO mini-pack; 2nd B = burn-in option 4000B : 4000V : 4000UB: HEC

74HCT 4013

Abstract: CD4078 4093 BF SN74368A SN74ALS679 LXZ Series 4069 CMOS hex inverter 2a2 vacuum tube CD74AC374 cd408
Contextual Info: SN54HC240, SN74HC240 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS128B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC240 . . . J OR W PACKAGE SN74HC240 . . . DW OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

IC 40106 pin diagram

Abstract: cmos ALL 4000- 4001- 4002 TO 4099 series IN MOTOROLA signetics hand book SDFD001B SN74368A cd4536 74HCT 4013 CD4000 SERIES BOOK SDLS051 40106 internal circuit diagram
Contextual Info: SN54ABT646A, SN74ABT646A OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUPUTS SCBS069G – JULY 1991 – REVISED MAY 1997 D D D D SN54ABT646A . . . JT OR W PACKAGE SN74ABT646A . . . DB, DW, NT, OR PW PACKAGE TOP VIEW CLKAB SAB DIR A1 A2 A3 A4 A5 A6 A7

SN502

Abstract: 74HCT 4013 SN74368A ic 4024 7-stage counter 163245 cd408 CD74AC374 1A2 CPU TSSOP 20PIN sn7414 circuit 4000 series CMOS Logic ICs 4030
Contextual Info: SN54F244, SN74F244 OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SDFS063A – D2932, MARCH 1987 – REVISED OCTOBER 1993 • SN54F244 . . . J PACKAGE SN74F244 . . . DB, DW, OR N PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

125c74

Abstract: TTL CI 7805 1A2 CPU TSSOP 20PIN SN74368A SN74BCT126 cmos 555 CD74AC374 cmos ALL 4000- 4001- 4002 TO 4099 series IN MOTOROLA TTL to LVTTL level shifter 5101 fb
Contextual Info: SN54HC244, SN74HC244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS SCLS130B – DECEMBER 1982 – REVISED MAY 1997 D D SN54HC244 . . . J OR W PACKAGE SN74HC244 . . . DB, DW, N, OR PW PACKAGE TOP VIEW 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers

IC 40106 pin diagram

Abstract: CD4000 SERIES BOOK hct 4047 bt IC 40106 pin sn 16861 7805 acv SN74HC or-gate ic HC 4066 AG SDAD001 SN74S124
Contextual Info: SN54ABT646, SN74ABT646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS SCBS068E – JULY 1991 – REVISED JULY 1994 • • • • • • State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per