CLOCKING Search Results

Contextual Info: 54AC11377, 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE TI0180— D3420, M A R C H 1990 Contains Eight D-Type Flip-Flops 54AC11377 . . . JT PACKAGE 74AC11377 . . . DW OR NT PACKAGE Clock Enable Latched to Avoid False Clocking TOP VIEW 1Q [ 2Q [ 3Q [

D3450

Contextual Info: 74ACT11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS129 - D3450, MARCH 1990 - REVISED APRIL 1993 • * Inputs Are TTL-Voltage Compatible DB, DW OR NT PACKAGE TOP VIEW I * Contains Eight D-Type Flip-Flops I I * Clock Enable Latched to Avoid False Clocking

TC8250P

Contextual Info: REAL TIME CLOCK TC8250P/AP Real Time Clock 1. INTRODUCTION The TC8250P or TC8250AP is a single chip C-MOS LSI for real time clock, which is composed as a peripheral LSI of a microcomputer. V The RTC has a 32768Hz X'tal oscillation circuit, counter group for clocking, control circuit for

d204d

Contextual Info: 74AC11377 OCTAL D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS101 - D3420, FEBRUARY 1990 - REVISED APRIL 1993 i * Contains Eight D-Type Flip-Flops * Clock Enable Latched to Avoid False Clocking DW OR NT PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern

Contextual Info: CD74HC4017-Q1 HIGH-SPEED CMOS LOGIC DECADE COUNTER/DIVIDER WITH 10 DECODED OUTPUTS SCLS546SA − OCTOBER 2003 − REVISED APRIL 2008 D D D D D D D Qualified for Automotive Applications Fully Static Operation Buffered Inputs Common Reset Positive Edge Clocking

Contextual Info: BCM8022 PRODUCT Brief XAUI TO 10GBASE-CX4 RETIMER B C M 8 0 2 2 F E AT U R E S • High-speed Retiming for transmission over copper interconnects such as Infiniband Cables or Backplanes • Multi-configurable to support various operating modes • 4 Independent 1.0 to 3.2-Gbps Retimers Single Clocking

Contextual Info: MX85xxxx Family Complete Clocking Solution with Integrated Crystal, Synthesizer, and Fanout ClockWorks Fusion General Description Features Micrel’s MX85xxxx family of parts are ultra-low phase noise clocking solutions that integrate the crystal, synthesizer, and fanout buffers, providing up to two

C1608X7R1H105K

Abstract: Sim card diagram CAPACITOR type 1uF RST 10
Contextual Info: MIC4555 SIM Card Level Shifter with 50mA LDO General Description Features The MIC4555 is a digital level shifter with a 50mA LDO for SIM Card interfaces. There are three high speed level shifters for SIM Card signal translation. The level shifters are designed to support high speed clocking up to 5MHz.

TCO-2112

Abstract: AD9516
Contextual Info: 14-Output Clock Generator AD9516-5 FEATURES APPLICATIONS Low jitter, low phase noise clock distribution Clock generation and translation for SONET, 10Ge, 10G FC, and other 10 Gbps protocols Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs High performance wireless transceivers

W182I

Abstract: W182-5GI W182GI
Contextual Info: W182I Full Feature Peak Reducing EMI Solution Industrial Temperature Features Table 1. Modulation Width Selection • Cypress PREMIS family offering • Generates an EMI optimized clocking signal at the output • Selectable output frequency range • Single 1.25% or 3.75% down W182I or center

delta plc program sample

Abstract: WM8739 WM8739EFL WM8739LEDS WM8739LEFL XWM8739EDS
Contextual Info: WM8739 / WM8739L Stereo Audio ADC DESCRIPTION FEATURES • • 90dB SNR ‘A’ weighted @ 48kHz ADC Low Power Stereo line-level audio inputs are provided, along with a mute and volume function, and master or slave mode clocking schemes. The device also has a programmable

verilog code for cdma transmitter

Abstract: Actel pdf on gsm Actel pdf on radio emitter CS180 AC212 AX250-PQ208 testbench of a transmitter in verilog
Contextual Info: Application Note AC212 Designing a SuperClock with an Axcelerator Device Introduction Many board designs today require complex clocking schemes involving multiple frequencies and phases. Semiconductor manufacturers have developed a multitude of products to address these situations, from

2N3904

Abstract: EL2020 SN28846 SN28846DW TC210 TL1591 TMS3473B TC2101
Contextual Info: TC210 192- x 165-PIXEL CCD IMAGE SENSOR SOCS009B – OCTOBER 1986 – REVISED MAY 1990 • • • • • • • • • • Full-Frame Operation Antiblooming Capability Single-Phase Clocking for Horizontal and Vertical Transfers Fast Clear Capability Dynamic Range . . . 60 dB Typical

T8538

Abstract: T8537
Contextual Info: Product Brief May 1999 T8537/T8538 Quad Programmable Codec Features • +3.3 V operation ■ Per-channel programmable gains, equalization, termination impedance, and hybrid balance ■ Programmable µ-law, linear, or A-law modes ■ Two programmable PCM ports with single and double clocking modes

Contextual Info: VF231C Crystal Oscillators LVPECL/LVDS 3.3V 5X7 mm Surface Mount 750 KHz to 800 MHz Description Valpey Fisher’s VF231C surface mount oscillators provide waveforms for clocking LVPECL and LVDS circuits. The 5X7mm footprint package provides the performance of larger oscillators with a level of board space reduction

Contextual Info: 74AC11378 HEX D–TYPE FLIP–FLOP WITH CLOCK ENABLE SCAS150 – APRIL 1991 – REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

MACH465

Contextual Info: CO ND ENSED COM’L: -12/15/20 MACH465-12/15/20 AdvaM n“¿ High-Density EE CMOS Programmable Logic Devices DISTINCTIVE CHARACTERISTICS • 208 pins in PQFP ■ Up to 20 product terms per function, with XOR ■ JTAG, 5-V, In-circuit programmable ■ Flexible clocking

Contextual Info: 74AC11378 HEX D-TYPE FLIP-FLOP WITH CLOCK ENABLE SCAS150 − APRIL 1991 − REVISED APRIL 1993 • • • • • • • • DW OR N PACKAGE Contains Six D-Type Flip-Flops Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage

ACT 12.288

Contextual Info: CS2300-OTP Fractional-N Clock Multiplier with Internal LCO Features General Description  Clock Multiplier / Jitter Reduction The CS2300-OTP is an extremely versatile system clocking device that utilizes a programmable phase lock loop. The CS2300-OTP is based on a hybrid analogdigital PLL architecture comprised of a unique combination of a Delta-Sigma Fractional-N Frequency

Contextual Info: CY24272 Rambus XDR Clock Generator with Zero SDA Hold Time Rambus‚ XDR™ Clock Generator with Zero SDA Hold Time Features • Table 1. Device Comparison Meets Rambus Extended Data Rate XDR™ clocking requirements ■ 25 ps typical cycle-to-cycle jitter

Contextual Info: ill# ICW 0RKS W180 Peak Reducing EMI Solution Features • IC WORKS PREMIS family offering • Generates an EMI optimized clocking signal at the output Key Specifications Supply Voltages: • Selectable output frequency range VDD = 3.3V±0.3V or VDD = 5V±10%

PLL72

Abstract: CY2907 CY2907PC CY2907SC
Contextual Info: fax id: 3521 J S 3 P *1" CY2907 PRELIMINARY OYi nhob = General Purpose Clock Synthesizer/Driver Features • Highly configurable single PLL clock synthesizer pro­ vides all clocking requirem ents for numerous applica­ tions • Com patible with all industry standard 9107 and 9108

Ultra37064

Abstract: CERAMIC LEADLESS CHIP CARRIER CY7C372 CY7C373 ieee1149.1 cypress
Contextual Info: J ^ m n rn n : if : Y PRELIMINARY H Ultra37064 - UltraLogic 64-Macrocell ISR™ CPLD Features — ts = 3.5 ns — tc o = 4.5 ns • 64 m a cro cells in fo u r logic blocks • P ro d uct-term clocking • In-S ystem R ep ro g ra m m ab le ™ IS R ™

HCF4032B

Abstract: HCF4032BEY HCF4032BM1 HCF4032M013TR PO13H
Contextual Info: HCF4032B TRIPLE SERIAL ADDER • ■ ■ ■ ■ ■ ■ ■ ■ INVERT INPUTS ON ALL ADDERS FOR SUM COMPLEMENTING APPLICATIONS FULLY STATIC OPERATION.DC TO 10MHz Typ. at VDD = 10V BUFFERED INPUTS AND OUTPUTS SINGLE PHASE CLOCKING QUIESCENT CURRENT SPECIFIED UP TO