CLOCK CONTROL Search Results

DC generator

Abstract: crystal controlled time base generator application MSP430
Contextual Info: MSP430 Family 7 Oscillator, System Clock Generator Oscillator and System Clock Generator Topic Page 7.1 Crystal Oscillator 7-4 7.2 Processor Clock Generator 7-4 7.3 System Clock Operating Modes 7-7 7.4 System Clock Control Register 7-9 7.5 DCO Characteristic - typical

encoder

Abstract: encoder/decoder decoder circuit diagram of encoder xtal decoder and encoder F3 diode
Contextual Info: DATA ENABLE ENCODER FORCE IDLE ENCODER OUTPUT ENCODER INPUT MOD VDD VSS f2 f1 XTAL/CLOCK fo XTAL ENCODER DATA CLOCK CLOCK RATE GENERATORS DECODER DATA CLOCK VBIAS MODE1 MODE2 CLOCK MODE LOGIC ALGORITHM POWERSAVE DECODER INPUT SAMPLING RATE CONTROL 3 or 4 BIT

encoder

Abstract: encoder/decoder decoder xtal circuit diagram of encoder 4 bit encoder algorithm application of decoder decoder and encoder decoder datasheet
Contextual Info: DATA ENABLE ENCODER FORCE IDLE ENCODER INPUT MOD VDD VSS ENCODER OUTPUT f2 f1 XTAL/CLOCK fo XTAL ENCODER DATA CLOCK CLOCK RATE GENERATORS DECODER DATA CLOCK VBIAS MODE1 MODE2 CLOCK MODE LOGIC ALGORITHM POWERSAVE DECODER INPUT SAMPLING RATE CONTROL 3 or 4 BIT

sm 0038 PIN DIAGRAM

Abstract: f control method P0C7
Contextual Info: SHARP SM8504/SM8506 SYSTEM CONTROL Oscillator Circuit The system clock, leads CPU operation, is one of The SM 8500 series is built-in the m ain-clock and the five clocks w hich divides the m ain-clock fcx sub-clock oscillator circuits fo r generating clock

Crystal oscillator 12 MHz

Abstract: CDC9449
Contextual Info: CDC9449 PC CLOCK SYNTHESIZER/DRIVER WITH SDRAM CLOCK SUPPORT SCAS577 – AUGUST 1996 D D D D D D D D DB PACKAGE TOP VIEW Utility Clock Generation for Personal Computer Applications Two 48-MHz Serial Bus Clock Outputs One 24-MHz Super I/O Controller Clock

encoder

Abstract: decoder datasheet CMX639 encoder/decoder decoder
Contextual Info: DATA ENABLE ENCODER FORCE IDLE ENCODER INPUT MOD VDD VSS f1 XTAL/CLOCK CLOCK RATE GENERATORS ENCODER DATA CLOCK DECODER DATA CLOCK VBIAS MODE 1 MODE 2 CLOCK MODE LOGIC ALGORITHM POWERSAVE f2 f0 XTAL SAMPLING RATE CONTROL f3 DECODER INPUT ENCODER OUTPUT 3 or 4 BIT

Contextual Info: PRELIMINARY CY2VC511 27 MHz Clock Generator with VCXO Features Description • Generates 27 MHz Output Clock ■ Uses 27 MHz LVCMOS Reference Clock ■ LVCMOS Output The CY2VC511 is a PLL based clock generator with VCXO control. It takes a low swing 27 MHz reference clock, and

CY29942

Abstract: CY29942AC CY29942ACT CY29942AI CY29942AIT MPC942C
Contextual Info: 42 CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz clock support 2.5V or 3.3V operation LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 200 ps max. output-to-output skew Output Enable control

MPC942C

Abstract: CY29942 CY29942AI
Contextual Info: 42 CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz Clock Support 2.5V or 3.3V Operation LVCMOS/LVTTL Clock Input LVCMOS/LVTTL Compatible Inputs 18 Clock Outputs: Drive up to 36 Clock Lines 200 ps max. Output to Output Skew Output Enable Control

Contextual Info: 42 CY29942 2.5V or 3.3V, 200-MHz, 1:18 Clock Distribution Buffer Features 200-MHz clock support 2.5V or 3.3V operation LVCMOS/LVTTL clock input LVCMOS-/LVTTL-compatible inputs 18 clock outputs: drive up to 36 clock lines 200 ps max. output-to-output skew Output Enable control

DIP28

Abstract: PLCC28 TS68950 TS68951 TS68952 TS68952CFN TS68952CP programming controle system with c rc711
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

TDC 8117

Abstract: TS68952CP
Contextual Info: TS68952 MODEM TRANSMIT/RECEIVE CLOCK GENERATOR . . . . . . INDEPENDANT TRANSMIT AND RECEIVE CLOCK GENERATORS WITH DIGITAL PHASE LOCKED LOOPS TRANSMIT DPLL SYNCHRONIZATION ON EXTERNAL TERMINAL CLOCK OR INTERNAL RECEIVE CLOCK RECEIVE DPLL SYNCHRONIZATION CONTROLLED FROM THE BUS

vhdl code for phase frequency detector

Abstract: vhdl code for DCM CLKFX180 dcm verilog code
Contextual Info: R Using Digital Clock Managers DCMs Overview Virtex-II devices have 4 to 12 DCMs, and each DCM provides a wide range of powerful clock management features: • Clock De-skew: The DCM contains a digitally-controlled feedback circuit (delaylocked loop) that can completely eliminate clock distribution delays. Clock de-skew

7B991

Abstract: 7B991RP
Contextual Info: 7B991 Programmable Skew Clock Buffer PSCB DESCRIPTION: • • • • • • • Maxwell Technologies’ 7B991 Programmable Skew Clock Buffers (PSCB) offer user-selectable control over system clock functions. These multiple-output clock drivers provide

7B991

Contextual Info: 7B991 Programmable Skew Clock Buffer PSCB FEATURES: DESCRIPTION: • • • • • • • Maxwell Technologies’ 7B991 Programmable Skew Clock Buffers (PSCB) offer user-selectable control over system clock functions. These multiple-output clock drivers provide

SAA7115

Abstract: SAA7112 ITU-601 "Video Decoder" SAF7113 LQFP100 PLCC68 QFP64 SAA7110A SAA7111A SAA7113
Contextual Info: Digital Video Decoders Your Digital Gateway to the Analog World Semiconductors Recommended for New Designs DEVICE Clock: Sample Rate Line-Locked Clock MPEG Compatible Clock Real-Time Control RTC Audio Clock Input: Analog Inputs Analog-to-Digital Converters (ADCs)

7B991

Abstract: 7B991RP
Contextual Info: 7B991 Programmable Skew Clock Buffer PSCB FEATURES: DESCRIPTION: • • • • • • • Maxwell Technologies’ 7B991 Programmable Skew Clock Buffers (PSCB) offer user-selectable control over system clock functions. These multiple-output clock drivers provide

7B991

Abstract: 7B991RP MIL-STD-882
Contextual Info: 7B991 Programmable Skew Clock Buffer PSCB FEATURES: DESCRIPTION: • • • • • • • Maxwell Technologies’ 7B991 Programmable Skew Clock Buffers (PSCB) offer user-selectable control over system clock functions. These multiple-output clock drivers provide

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8113 is a single clock generator IC with an integrated PLL. It can generate either a 74.17582MHz or a 74.25MHz clock from a 27MHz master clock input frequency. Through pin control,

vhdl code for phase frequency detector

Abstract: vhdl code for multiplexer 64 to 1 using 8 to 1 vhdl code for DCM vhdl code for Digital DLL
Contextual Info: R Chapter 2: Design Considerations Digital Clock Managers DCMs Overview Virtex-II Pro devices have four to eight DCMs, and each DCM provides a wide range of powerful clock management features: • Clock De-skew: The DCM contains a digitally-controlled feedback circuit (delaylocked loop) that can completely eliminate clock distribution delays. Clock de-skew

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8111 is a single clock generator IC with an integrated PLL. It can generate either a 12.288MHz or a 24.576MHz clock from a 27MHz master clock input frequency. Through pin control,

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8114 is a single clock generator IC with an integrated PLL. It can generate either a 33.333MHz or a 48.000MHz clock from a 27MHz master clock input frequency. Through pin control,

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8115 is a single clock generator IC with an integrated PLL. It can generate either a 27.0MHz or 74.17582MHz clock from a 41.538MHz master clock input frequency. Through pin control, the

24bit rgb input to 8bit ITU output

Abstract: ITU-601 SAA7115 ITU601 LQFP100 SAA7110A SAA7111A SAA7112 SAA7113 SAA7114
Contextual Info: Philips Semiconductors NEW SAA7115 Your Digital Gateway to the Analog World Digital Video Decoders from the World Leader DEVICE Clock: Sample Rate Line-Locked Clock MPEG Compatible Clock Real-Time Control RTC Audio Clock Input: Analog Inputs Analog-to-Digital