CLOCK CONTROL Search Results

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8111 is a single clock generator IC with an integrated PLL. It can generate either a 12.288MHz or a 24.576MHz clock from a 27MHz master clock input frequency. Through pin control,

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8114 is a single clock generator IC with an integrated PLL. It can generate either a 33.333MHz or a 48.000MHz clock from a 27MHz master clock input frequency. Through pin control,

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8115 is a single clock generator IC with an integrated PLL. It can generate either a 27.0MHz or 74.17582MHz clock from a 41.538MHz master clock input frequency. Through pin control, the

Contextual Info: HD74AC107/HD74ACT107 Description with Separate Clear and Clock Pin Assignment The HD74AC107/HD74ACT107 dual JK master/ slave flip-flops have a separate clock for each flipflop. Inputs to the master section are controlled by the clock pulse. The clock pulse also regulates the

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Features Description The AK8118 is a single clock generator IC with an integrated PLL. It can generate either a 40.5MHz or a 32.0MHz clock from a 27MHz master clock input frequency. Through pin control, the output

Contextual Info: ASAHI KASEI EMD CORPORATION Single Clock Generator Description Features The AK8112 is a single clock generator IC with an integrated PLL. It can generate either a 33.75MHz or a 67.5MHz clock from a 27MHz master clock input frequency. Through pin control, the output

MS-001

Abstract: High Tech Chips
Contextual Info: HIGH TECH CHIPS, INC. General Description HTC2503 is analog clock controller IC. It is designed to replace clock driver chips in wall mount clocks. It's versatile design allows it to be used in range of clock application ranging from simple wall clocks to centralized clock controllers for

XTAL 27.0000MHZ

Abstract: 22.5792 crystal oscillator 4 pins 33.8688 MHz crystal clock generator 33.8688 MHz crystal oscillator clock SM8707 SM8707DV SM8707EV HP54701A
Contextual Info: SM8707 series Clock Generator with Dual PLLs OVERVIEW The SM8707 series are dual-PLL clock generator ICs, using a 27MHz master clock, that generate independent audio clock, video clock, and signal processor clock outputs needed in DVD player/recorder applications. Each

HTC2502

Abstract: MS-001
Contextual Info: HIGH TECH CHIPS, INC. General Description HTC2502 is analog clock controller IC. It is designed to replace clock driver chips in wall mount clocks. It's versatile design allows it to be used in range of clock application ranging from simple wall clocks to centralized clock controllers for

CD82C85

Abstract: 80C86 80C88 82C85 CS82C85 ID82C85 IS82C85 74HCxx logic table
Contextual Info: 82C85 CMOS Static Clock Controller/Generator March 1997 Features Description • Generates the System Clock For CMOS or NMOS Microprocessors and Peripherals The Intersil 82C85 Static CMOS Clock Controller/Generator provides complete control of static CMOS system operating modes and supports full speed, slow, stop-clock and

MK1707

Abstract: MK1707S MK1707STR
Contextual Info: PRELIMINARY INFORMATION MK1707 Low EMI Clock Generator I C R O C LOC K Description Features The MK1707S generates a low EMI output clock from a clock input. The part is designed to dither the LCD interface clock for flat panel graphics controllers. The device uses ICS/MicroClock’s

XRK7955

Contextual Info: xr XRK7955 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER MARCH 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK7955 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

75MHZ

Abstract: XRK799J93 XRK799J93IQ
Contextual Info: xr XRK799J93 INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER DECEMBER 2006 REV. 1.0.1 GENERAL DESCRIPTION The XRK799J93 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

XRK79892

Abstract: XRK79892IQ
Contextual Info: xr XRK79892 PRELIMINARY INTELLIGENT DYNAMIC CLOCK SWITCH PLL CLOCK DRIVER JANAUARY 2005 REV. P1.0.1 GENERAL DESCRIPTION The XRK79892 is a PLL clock driver designed specifically for redundant clock tree designs. The device receives two differential LVPECL clock signals

Contextual Info: EDI2GG41864V 576 Kilobyte Synchronous Card Edge DIMM FEATURES • 4x64Kx18 Synchronous • Flow-Through Architecture • Clock Controlled Registered Bank Enables E1\, E2\, E3, E4\ • Clock Controlled Registered Address • Clock Controlled Registered Global Write (GW\)

CY7B9911V

Abstract: 7B9911V-8
Contextual Info: CY7B9911V 3.3V RoboClock+ High-Speed Low-Voltage Programmable Skew Clock Buffer LV-PSCB Features selectable control over system clock functions. These multipleoutput clock drivers provide the system integrator with functions necessary to optimize the timing of high-performance

405C

Abstract: LVEP224 NB100LVEP224 LQFP-64 thermal pad
Contextual Info: NB100LVEP224 2.5V/3.3V 1:24 Differential ECL/PECL Clock Driver with Clock Select and Output Enable http://onsemi.com Description The NB100LVEP224 is a low skew 1−to−24 differential clock driver, designed with clock distribution in mind, accepting two clock

Contextual Info: GA11 1 0 M ulti-Phase Clock G enerator Low -Skew TTL Clock Buffer r gazelle Features G eneral Description Gazelle’s GA1110 is a low-skew TTL-level clock buffer chip with : multi-phase clock generation. It produces multiple clock outputs which are phase and frequency synchronized to a periodic clock

Contextual Info: xr XRK4991 PRELIMINARY 3.3V HIGH-SPEED 80 MHZ PROGRAMMABLE SKEW CLOCK BUFFER MARCH 2005 REV. P1.0.2 FUNCTIONAL DESCRIPTION The XRK4991 3.3V High-Speed Low-Voltage Programmable Skew Clock Buffer offers user selectable control over system clock functions to

74FXX

Abstract: P702-01XC PLL702-01XC PLL702-01XCL PLL702-01XCLR PLL702-01XC-R ASIC2
Contextual Info: PLL702-01 Clock Generator for PowerPC Based Applications FEATURES • • • • • • • 1 CPU Clock output with selectable frequencies 50, 66, 75, 80, 83, 90, 100,125 or 133 MHz . 1 ASIC output clock (at CPU clock or CPU clock ÷ 2). 2 ASIC output clocks (at CPU clock) w/ output enable.

Contextual Info: CY29940 2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer 2.5 V or 3.3 V, 200-MHz, 1:18 Clock Distribution Buffer Features Description • 200-MHz clock support ■ LVPECL or LVCMOS/LVTTL clock input ■ LVCMOS/LVTTL compatible inputs ■ 18 clock outputs: drive up to 36 clock lines

FS6128-01

Contextual Info: FS6128-01 PLL Clock Generator IC with VCXO AMERICAN MICROSYSTEMS, INC. April 2000 1.0 Features 2.0 • Phase-locked loop PLL device synthesizes output clock frequency from crystal oscillator or external reference clock • On-chip tunable voltage-controlled crystal oscillator

0314c

Abstract: 45 MHz clock oscillator RC001
Contextual Info: RC001 RC001 Redundant Clock Module Positive ECL Compatible Differential Output U.S. Patent 6,970,045 0314C Rev F Description The Redundant Clock Module is intended to supply highly reliable fixed clock reference. This clock output is based on two clock references internal that are monitored and eliminated

LVEP221

Abstract: MC100EP221 NB100LVEP221
Contextual Info: NB100LVEP221 2.5V/3.3V 1:20 Differential HSTL/ECL/PECL Clock Driver Description The NB100LVEP221 is a low skew 1−to−20 differential clock driver, designed with clock distribution in mind, accepting two clock sources into an input multiplexer. The two clock inputs are differential