CLK 503 Search Results

ic 8155 block diagram

Contextual Info: Lattice Specifications GAL6002B fmax DESCRIPTIONS CLK CLK fm ax w ith External Feedback 1/ tsu+tco Note: fmax with external feedback is calculated from measured tsu and tco. 4- to -M 4- tpd- W

Contextual Info: SN54HC166, SN74HC166 8-BIT PARALLEL-LOAD SHIFT REGISTERS SCLS117B – DECEMBER 1982 – REVISED MAY 1997 description The ’HC166 parallel-in or serial-in, serial-out registers feature gated clock CLK, CLK INH inputs and an overriding clear (CLR) input. The

hsm2812

Abstract: ANSI-644 ADA4937-2 AN-835 TC1-1-13M IEEE-1596 TC1-1-13M equivalent murata LTE band pass filter
Contextual Info: 10 MHz Bandwidth, 640 MSPS Dual Continuous Time Sigma-Delta Modulator AD9267 FEATURES AVDD PDWNB PDWNA DRVDD LVDS DRIVERS OR±A VIN+A Σ-Δ MODULATOR VIN–A D3±A D0±A PLL_LOCKED VREF CFILT AD9267 PLLMULT4 PLLMULT3 PLLMULT2 PHASELOCKED LOOP CLK+ CLK– DCO±

Contextual Info: 7672 12-Bit A/D Converter VREF AIN1 AIN2 2 1 24 + - 12-BIT DAC + - SUCCESSIVE APPROXIMATION REGISTER 12-BIT LATCH CONTROL LOGIC 23 VDD 22 VSS 21 BUSY 20 CS 19 RD 18 CLK OUT 17 CLK IN THREE-STATE OUTPUT DRIVERS CLOCK OSCILLATOR 3 4 11 12 13 16 AGND D11 D4 DGND

TQ6122AM

Abstract: TQ611 TQ6122-M 2291C DAC-IC lm337mt MC33071 TQ6122 TQ6122-D MC1403A
Contextual Info: T R I Q U BLANK I N T A5 A4 A0 B0 S E M I C O N D U C T O R, I N C . B4 B5 TQ6122 A7 MSB A6 B6 B7 ECL INPUT BUFFERS MULTIPLEXER V SS (-5 V) D DGND CLK CLK BLANKING LOGIC Q BLANK D0 D4 D5 D6 D7 QBLANK Q0 Q4 Q5 Q6 Q7 + – MASTER LATCH Features BINARY-TO-N-OF-7

GAL20LV8ZD

Abstract: GAL20LV8ZD-15QJ GAL20LV8ZD-25QJ GAL20V8
Contextual Info: Specifications GAL20LV8ZD GAL20LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

GAL20LV8ZD

Abstract: GAL20LV8ZD-15QJ GAL20LV8ZD-25QJ GAL20V8
Contextual Info: Specifications GAL20LV8ZD GAL20LV8ZD Low Voltage, Zero Power E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • 3.3V LOW VOLTAGE, ZERO POWER OPERATION — JEDEC Compatible 3.3V Interface Standard — Interfaces with Standard 5V TTL Devices

16v8z

Abstract: 16V8ZD
Contextual Info: GAL16V8Z GAL16V8ZD I Semiconductor I Corporation Zero Power E2CMOS PLD l/CLK - > - ZERO POWER E2CMOS TECHNOLOGY — 100jjA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down

20L10

Abstract: 20XV10 GAL20XV10 GAL20XV10B-10LJ GAL20XV10B-10LP PAL12L10
Contextual Info: Specifications GAL20XV10 GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output

GAL20XV10B-10LP

Abstract: 20L10 20XV10 GAL20XV10 GAL20XV10B-10LJ PAL12L10
Contextual Info: Specifications GAL20XV10 GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES I/CLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output

16v8z

Abstract: gal16v8z GAL16V8 GAL16V8Z-12QJ GAL16V8Z-12QP
Contextual Info: GAL16V8Z GAL16V8ZD Zero Power E2CMOS PLD Functional Block Diagram Features I/CLK • ZERO POWER E2CMOS TECHNOLOGY — 100 A Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down

JT-G703

Abstract: 1N4148 1N914 AN-517 PE-65966 PE-65969 TXC-02050C HDB3 coding EQB-0
Contextual Info: Proprietary TranSwitch Corporation Information for use Solely by its Customers MRT TXC-02050C DATA SHEET BLOCK DIAGRAM LINE SIDE TERMINAL SIDE EQB1 EQB0 LOW VAGC GNDA AGFIL RXLOS VCOC PLLC PNENB RXDIS + RP/RD HDB3 - RN Decoder clk + DI1 DI2 Equalization Network

GAL programmer schematic

Abstract: 26CV12 GAL26CLV12 GAL26CLV12D-5LJ GAL26CLV12D-7LJ
Contextual Info: GAL26CLV12 FEATURES Features Functional Block Diagram • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 5 ns Maximum Propagation Delay — Fmax = 200 MHz — 3.5 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology I/CLK INPUT RESET

16V8Z

Abstract: 16V8ZD K 2056 transistor GAL16V8 GAL16V8Z GAL16V8Z-12QJ GAL16V8Z-12QP XOR-2048
Contextual Info: GAL16V8Z GAL16V8ZD Zero Power E2CMOS PLD Functional Block Diagram Features I/CLK • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down

16L8* GAL

Abstract: pin diagram of xor 16l8 JEDEC fuse 16v8z 2123 16 pin diagram gal programming specification K 2056 transistor GAL16V8 GAL16V8Z GAL16V8Z-12QJ
Contextual Info: GAL16V8Z GAL16V8ZD Zero Power E2CMOS PLD Functional Block Diagram Features I/CLK • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down

Contextual Info: TM TM ispGDX and ispGDS Architectural Description combinatorial outputs. Each I/O cell has individual, programmable tri-state control OE , register or latch clock, (CLK), and programmable polarity. The OE control for each I/O pin is independent and may be driven via the

20XV10

Abstract: 20L10 GAL20XV10 GAL20XV10B-10LJ GAL20XV10B-10LP PAL12L10
Contextual Info: Specifications GAL20XV10 GAL20XV10 High-Speed E2CMOS PLD Generic Array Logic FUNCTIONAL BLOCK DIAGRAM FEATURES 2 I/CLK • HIGH PERFORMANCE E CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 100 MHz — 7 ns Maximum from Clock Input to Data Output

Contextual Info: GAL20XV10 Lattica High-Speed E2CMOS PLD Generic Array Logic Semiconductor Corporation FUNCTIONAL BLOCK DIAGRAM FEATURES l/CLK □ - • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax =100 MHz — 7 ns Maximum from Clock Input to Data Output

S0-7803

Abstract: 26v12 GAL26V12 TWL 3016 GAL26V12C-10LJ GAL26V12C-10LP GAL26V12C-15LJ GAL26V12C-20LP GAL26V12C-7LJ Pin Diagrams 7809
Contextual Info: GAL26V12 High Performance E2CMOS PLD Generic Array LogicTM FEATURES FUNCTIONAL BLOCK DIAGRAM I/CLK 1 8 8 INPUT I/O/Q OLMC 2 I/O/Q 12 INPUT INPUT INPUT • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability INPUT • APPLICATIONS INCLUDE:

M16C450

Abstract: M16550A baud rate generator vhdl
Contextual Info: Inventra M16x50-B1 Enhanced 16550A-Compatible UART Serial Communications FPGA/CPLD IP D A T A S H E E T CLK RCLK RCLK_BAUD BAUD BAUD RATE GENERATOR M16x50 key features: • Compatible with Inventra™ BRGE M16C450 and M16550A UARTs FIFO A[2:0] TRANSMIT

GAL16V8

Abstract: GAL16V8D GAL16V8D pin configuration 16l8 JEDEC fuse 16V8 GAL16V8D-10QJ GAL16V8D-10QP GAL16V8D-3LJ GAL16V8D-5LJ GAL16V8D-7LJ
Contextual Info: GAL16V8 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram I/CLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology

ci 7809

Abstract: GAL26V12 TWL 3016 26V12 GAL26V12C-10LJ GAL26V12C-10LP GAL26V12C-15LJ GAL26V12C-20LJ GAL26V12C-20LP ci 7814
Contextual Info: GAL26V12 High Performance E2CMOS PLD Generic Array LogicTM FEATURES FUNCTIONAL BLOCK DIAGRAM I/CLK 1 8 8 INPUT I/O/Q OLMC 2 I/O/Q 12 INPUT INPUT INPUT • PRELOAD AND POWER-ON RESET OF REGISTERS — 100% Functional Testability INPUT • APPLICATIONS INCLUDE:

GAL20V8B

Abstract: GAL20V8 gal 20v8 programming specification lattice GAL20V8 20V8 5962-8984004LA gal programming specification 05a10
Contextual Info: GAL20V8/883 High Performance E2CMOS PLD Generic Array Logic Features Functional Block Diagram I/CLK • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 10 ns Maximum Propagation Delay — Fmax = 62.5 MHz — 7 ns Maximum from Clock Input to Data Output — TTL Compatible 12 mA Outputs

TQ1136-06M

Abstract: TQ1136-12M d642
Contextual Info: PRODUCT INFORMATION TriQuint Q-LOGIC 1:12 DEM ULTIPLEXER TQ 1136-12M T Q 1136-06M FEATURES 1.2 G bits/sec NRZ Data Rate TQ1I36-12M Fram e Shift C apability ECL-Compatible Inputs and Outputs Fully Compatible w ith TQ1135 M ultiplexer BLOCK DIAGRAM CLK Q -NCLK