CLEAR LOGIC Search Results

PID control

Abstract: CRC-16 GenerateReverseCrc16OnString SetIoUnitScratchPadInt32Element
Contextual Info: Digital Point Note: Commands with an asterisk* are available only in ioControl Professional. ioControl Command Clear All Latches Clear Counter Clear Off-Latch Clear On-Latch Generate N Pulses* Get & Clear Counter Get & Clear Off-Latch Get & Restart Off-Pulse Measurement*

HCF40XX

Abstract: 40162 cmos 40160B 40161B 40162B 40163B HCC40160B HCF40160B hcf40 HCC40161B
Contextual Info: HCC/HCF40160B-40161B HCC/HCF40162B-40163B SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS 40160B CLEAR 40161B CLEAR 40162B CLEAR 40163B CLEAR . . . . . . - DECADE WITH ASYNCHRONOUS - BINARY WITH ASYNCHRONOUS - DECADE WITH SYNCHRONOUS - BINARY WITH SYNCHRONOUS

74HC163

Abstract: 74HC160 74HC161 74HC162 MM54HC161 MM54HC162 MM54HC163 MM74HC160 MM74HC161 MM74HC160N
Contextual Info: MM74HC160 Synchronous Decade Counter with Asynchronous Clear MM54HC161 MM74HC161 Synchronous Binary Counter with Asynchronous Clear MM54HC162 MM74HC162 Synchronous Decade Counter with Synchronous Clear MM54HC163 MM74HC163 Synchronous Binary Counter with Synchronous Clear

74160 4-bit Decade Counter Asynchronous reset

Abstract: 74162 truth table 74163 8 bit COUNTER Truth Table 74163 Synchronous 74163 TC40163 74162 LOAD TC40160BP Truth Table 74161 TC40160
Contextual Info: a r g TC40160BP, TC40161 BP, U TC40162BP, TC40163BP • " 81 CIRCUIT SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTER TC40160BP DECADE WITH ASYNCHRONOUS CLEAR TC40161BP BINARY WITH ASYNCHRONOUS CLEAR TC40I62BP DECADE WITH SYNCHRONOUS CLEAR TC4Q163BP BINARY WITH SYNCHRONOUS CLEAR_

Contextual Info: GD54/74LS123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH CLEAR Feature Pin Configuration • • D-C Triggered from active-hign or active-low gated logic inputs Retriggerable for very long output pulses, up to 100% duty cycle • Overriding clear terminates output pulse

Contextual Info: GD54/74LS123 DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH CLEAR Feature Pin Configuration • • D-C Triggered from active-high or active-low gated logic inputs Retriggerable for very long output pulses, up to 100% duty cycle • Overriding clear terminates output pulse

DM54LS174

Abstract: 54LS174 54LS174DMQB 54LS174FMQB 54LS175 DM54LS175 DM74LS174 DM74LS175 LS174 LS175
Contextual Info: 54LS174 DM54LS174 DM74LS174 54LS175 DM54LS175 DM74LS175 Hex Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic All have a direct clear input and the quad 175 versions feature complementary

NTE74LS74A

Abstract: NTE7483 NTE74LS76A NTE7475 NTE7472 NTE7473 NTE7474 NTE74C74 NTE74H73 NTE74LS73
Contextual Info: INTEGRATED CIRCUITS - TTL TRANSISTOR TRANSISTOR LOGIC NTE74H71 14-Lead DIP, See Diag. 247 AND Gated J-K Master/Slave Flip-Flop “ /Preset & Clear Q 14-Lead DIP, See Diag. 247 NTE7472, NTE74H72 AND Gated J-K Master/Slave Flip-Flop “ /Preset & Clear Vcc

Contextual Info: TC74VHC161,163FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VHC161FN,TC74VHC163FN Synchronous Presettable 4-Bit Counter TC74VHC161FN Binary, Asynchronous Clear TC74VHC163FN Binary, Synchronous Clear Note: xxxFN JEDEC SOP is not available in

DM54LS174

Contextual Info: & June 1989 54LS174/DM54LS174/DM74LS174, 54LS175/DM54LS175/DM74LS175 Hex/Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary

DM74LS174

Abstract: DM74LS174M DM74LS174N DM74LS174SJ DM74LS175 DM74LS175M DM74LS175N DM74LS175SJ M16A M16D
Contextual Info: Revised April 2000 DM74LS174 • DM74LS175 Hex/Quad D-Type Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary

54LS174

Abstract: 54LS174DMQB 54LS174FMQB 54LS174LMQB 54LS175 LS174 LS175 DM74LS174
Contextual Info: DM74LS174/DM74LS175 Hex/Quad D Flip-Flops with Clear General Description Features These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a direct clear input, and the quad 175 versions feature complementary outputs from each flip-flop.

Contextual Info: TC74HC161_163AFN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC161AFN TC74HC163AFN Synchronous Presettable 4-Bit Counter TC74HC161AFN Binary, Asynchronous Clear TC74HC163AFN Binary, Synchronous Clear The TC74HC161A and 163A are high speed CMOS BINARY

Contextual Info: TC74ACT161_163FN TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT161FN,TC74ACT163FN Synchronous Presettable 4-Bit Binary Counter TC74ACT161P/F/FN Asynchronous Clear TC74ACT163P/F/FN Synchronous Clear Note: xxxFN JEDEC SOP is not available in

Contextual Info: High-Speed CMOS Logic MN74HC Series M N74HC174/M N74HC174S MN74HC174 MN74HC174S Hex D-Type F lip -F lop s with Clear • Description P -3 M N74HC174/M N74H C174S contain six hex D-type flip-flop circuits w ith clear in one chip, and this master/slave flip-flop has

Contextual Info: TC74HC161,163AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC161AP,TC74HC161AF TC74HC163AP,TC74HC163AF Synchronous Presettable 4-Bit Counter TC74HC161AP/AF Binary, Asynchronous Clear TC74HC163AP/AF Binary, Synchronous Clear The TC74HC161A and 163A are high speed CMOS BINARY

Contextual Info: SN54F175, SN74F175 QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR SDFS058A- 02932, MARCH 1987 - REVISED OCTOBER 1993 Contain Four Flip-Flops With Double-Rail Outputs Buffered Clock and Direct Clear Inputs Applications Include: Buffer/Storage Registers Shift Registers

54175

Abstract: 54174DMQB 54174FMQB DM54174J DM54174W DM74174 DM74174N DM74175 J16A N16E
Contextual Info: EM ICONDUCTQ R t DM74174, DM74175 Hex/Quad D Flip-Flops with Clear 175 contains fo u r flip-flops w ith double-rail outputs General Description These positive-edge triggered flip-flops utilize T T L circuitry to im plem ent D -type flip-flop logic. All have a direct clear input,

Contextual Info: TC74ACT161,163P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT161P,TC74ACT161F TC74ACT163P,TC74ACT163F Synchronous Presettable 4-Bit Binary Counter TC74ACT161P/F/FN Asynchronous Clear TC74ACT163P/F/FN Synchronous Clear The TC74ACT161 and T163 are advanced high speed CMOS

1N3064

Abstract: 1N916
Contextual Info: TECHNICAL DATA IN74123 Dual Monostable Multivibrator with Clear The IN74123 multivibrator feature d-c triggering from gated lowlevel-active A and high-level-active (B) inputs, and also provide overriding direct clear inputs. Complementary outputs are provided. The

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT

74ACT11867

Abstract: BOX655303
Contextual Info: 74ACT11867 SYNCHRONOUS 8-BIT UP/DOWN BINARY COUNTER WITH ASYNCHRONOUS CLEAR SCAS178 - D3990, DECEMBER 1991 - REVISED APRIL 1993 DW PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Asynchronous Clear Fully Independent Clock Circuit Simplifies Use Flow-Through Architecture Optimizes

TC7MH161FK

Abstract: TC7MH163FK
Contextual Info: TC7MH161,163FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MH161FK,TC7MH163FK Synchronous Presettable 4-Bit Binary Counter TC7MH161FK Asynchronous Clear TC7MH163FK Synchronous Clear The TC7MH161FK and 163FK are advanced high speed CMOS synchronous presettable 4-bit binary counters fabricated with

ctrdiv16

Abstract: t163
Contextual Info: TOSHIBA TC74ACT161/163 Synchronous Presettable 4-bit Counter 161: Binary, Asynchronous Clear 163: Binary, Synchronous Clear Features: • The TC74AC161 and T163 are advanced high speed CMOS SYNCHRONOUS PRESETTABLE 4-BIT BINARY COUNTERS fabricated w ith silicon gate and double-layer