HD74HC1 Search Results

Contextual Info: HITACHI/ LO GIC/A R R A Y S/ M E M TE HD74HC194 DË J 4 4 ^ 2 0 3 001044 3 5 J ~ 92D 1 0 4 4 3 # 4-bit Bidirectional Universal Shift Register This bidirectional sh ift register is designed to incorporate P IN A R R A N G M E N T v irtu a lly all o f the features a system designer may w ant in

Contextual Info: HITACHI/ L O G I C / A R RA YS /M EM T2 , _ . D E I 4MtihSD3 001D37S 0 | ~ ~ 92D HD74HC123A # Dual Retriggerable Monostable Multivibrators with Clear This multivibrator features both a negative. A, and a positive, • PIN ARRANGEMENT B, transition triggered input, either of which can be used as

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEM Ì2 dÊ J 44^303 0D1D44L. A | - HD74HC195 92D 10446 # 4-bit Parallel-Access Shift Register This shift register feetures parallel inputs, parallel outputs, J-K serial inputs, S hift/L oad control input, and a direct | D T- Hb -O l-ß S

Contextual Info: Ì5 HITACHI/ LOGIC/ARRAYS/MEM DE] 4 4 ^ 5 0 3 0GlD3b3 92D HD74HC107 4 |~ V T ~ lf b ~ '0 7 - '0 7 10363 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse.

Contextual Info: HITACHI/ L O G IC /A RRAYS/ NEN ^2 D E I 4 4 ^ 5 0 3 GD1D413 4 J ~ 92D HD74HC165 # 10413 Parallel-load 8-bit Shift Register This 8-bit serial shift register shifts data fro m Q A to Q h T-46-09-05 PIN ARRANGEMENT when clocked. Parallel inputs to each stage are enabled by a

Contextual Info: HITACHI/ L OGI C / ARR AY S / f l E N TS D È I 4 4 tï b 2 G 3 92D HD74HC14 DD10331 5 10331 r-n-zi D # Hex Schmitt-trigger Inverters • FEATURES I PIN ARRANGEMENT • High Speed Operation: fp^-10.5ns typ. C/."60pF • High Output Current: Fenout of 10 LSTTL Loads

Contextual Info: HITACHI/ LOGIC/AR RAYS/Î1EN ‘ÌH ï>Ëj 4 4 ^ 5 0 3 0010311 1 J ~ 92D HD74HC148 The HD74HC148 T -< û7 - ^ ‘ - 5 7 # 8-to-3-line Octal Priority Encoder encodes eight date 4 -2-1 binary (octal). 10391 lines to three-line | PIN ARRANGEMENT Cascading circuitry (enable input El

Contextual Info: H I T A C H I / LOGI C / A R R A Y S/ M E M =12 » E g 44LlbdÏÏd“ üGl D4QS S | ~ — . 92 D HD74HC160 HD74HC161 HD74HC162 HD74HC163 1040 5 D I ~ ^ S - Z 3 -0 5 # HD74HC160-Synchronous Decade Counter D ire c t Clear

Contextual Info: H I T A C H I / LOGIC/ARRAYS/riEfl TE D Ê | 4 4^^5 03 0 □ 1 □ 4 01 ô |~~ 92D HD74HC155 # 10401 D T 'iû ^ - a i >55" Dual 2-to-4-line Decoders/Dem ultiplexers This circuit features dual 1-line-to-4-line dem ultiplexer with | I PIN ARRANGEMENT individual strobes and common binary-address input. When

Contextual Info: HITACHI/ L O G I C / A R R A Y S / M E M 12 HD74HC157 HD74HC158 B E I 4iHbaG3 0P104CI3 1 | ~ . 92D 1 04 03 D 7 ^ 7 -.2 /-£ / # Quad. 2-to-1-line Data Selectors/Multiplexers with noninverted outputs # Quad. 2-to-l-line Data Selectors/Multiplexers (with inverted outputs)

Contextual Info: HITACHI/ LOGIC/ARRAYS/HEM ÌE Î ËJ 44Tb203 DOlOBñT D 92D HD74HC147 Ü J ~ -¿ 7 - 2 l~ S 7 10389 0 10-to-4-line Priority Encoder The H D 7 4 H C 1 4 7 features priority encoding of the inputs to ensure that only the highest order data line is encoded. Nine

HD74HC165P

Abstract: HD74HC165 HD74HC165FPEL PRDP0016AE-B PRSP0016DH-B
Contextual Info: HD74HC165 Parallel-load 8-bit Shift Register REJ03D0581-0300 Rev.3.00 Jan 31, 2006 Description This 8-bit serial shift register shifts data from QA to QH when clocked. Parallel inputs to each stage are enabled by a low level at the Shift/Load input. Also included is a gated clock input and a complementary output from the eighth bit.

Hitachi DSA0076

Abstract: HD74HC1G32 HD74HC32
Contextual Info: HD74HC1G32 2–input OR Gate ADE-205-313B Z 3rd. Edition April 2001 Description The HD74HC1G32 is high speed CMOS two input OR gate using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal circuit of

Hitachi DSA00279

Contextual Info: HD74HC138 3-to-8-line Decoder/Demultiplexer Description The HD74HC138 has 3 binary select inputs A, B and C . If the device is enabled these inputs determine which one of the eight normally high outputs will go low. Two active low and one active high enables (G1, G2A and G 2B) are provided to ease the cascading of decoders.

HD74HC107

Abstract: Hitachi DSA00279
Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is

Hitachi DSA00279

Contextual Info: HD74HC194 4-bit Bidirectional Universal Shift Register Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial

Hitachi DSA00279

Contextual Info: HD74HC148 8-to-3-line Octal Priority Encoder Description The HD74HC148 encodes eight data lines to three-line 4-2-1 binary (octal). Cascading circuitry (enable input EI and enable output EO) is provided to allow octal expansion without the need for external circuitry. The data inputs and outputs are active at the low logic level.

HD74HC04

Abstract: Hitachi DSA0076 HD74HC1G04
Contextual Info: HD74HC1G04 Inverter ADE-205-311B Z 3rd. Edition April 2001 Description The HD74HC1G04 is high speed CMOS inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed equivalent to LS–TTL series. The internal circuit of three stages

HD74HC04

Abstract: HD74HC1G04 HD74HC1G04CME
Contextual Info: HD74HC1G04 Inverter REJ03D0184–0500Z Previous ADE-205-311C (Z Rev.5.00 Jan.27.2004 Description The HD74HC1G04 is high-speed CMOS inverter using silicon gate CMOS process. With CMOS low power dissipation, it provides high-speed equivalent to LS–TTL series. The internal circuit of three stages

Contextual Info: HD74HC113 Dual J-K Flip-Flops with Preset REJ03D0563-0200 (Previous ADE-205-436) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and

HD74HC139RPEL

Abstract: HD74HC139P HD74HC139TELL PRDP0016AE-B TSSOP-16 HD74HC139 HD74HC139FPEL
Contextual Info: HD74HC139 Dual 2-to-4-line Decoders/Demultiplexers REJ03D0571-0300 Rev.3.00 Mar 25, 2009 Description The HD74HC139 contains two independent two-to-four-line decoders each with a single active low enable input 1G or 2G . Data on the select inputs (1A and 1B or 2A and 2B) cause one of the four normally high outputs to go low.

HD74HC194

Abstract: HD74HC194P PRDP0016AE-B
Contextual Info: HD74HC194 4-bit Bidirectional Universal Shift Register REJ03D0589–0200 Previous ADE-205-466 Rev.2.00 Jan 31, 2006 Description This bidirectional shift register is designed to incorporate virtually all of the features a system designer may want in a shift register. It features parallel inputs, parallel outputs, right shift and left shift serial inputs, operating mode control

ecg 6250 50

Abstract: HD74HC1G66 HD74HC4066 Hitachi DSA00187
Contextual Info: HD74HC1G66 Analog Switch ADE-205-314C Z 4th. Edition November 2000 Description The HD74HC1G66 is high speed CMOS analog switch using silicon gate CMOS process. With CMOS low power dissipation, it provides high speed. The device has low ON resistance for good transfer

R16-14

Contextual Info: HD74HC107 # Dual J-K Flip-Flops with Clear This flip -flo p is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and