CICO NO 3 Search Results

Contextual Info: H CATALOG MICRO SWITCH D IV IS IO N OF BZ-2RQ1 S W IT C H -B A S IC F R E E P O R T . IL L IN O IS . U .S .A . A HO NEYW ELL L IS T IN G F ED . M FG . C O D E 9 1 9 2 9 HARDENED STEEL PLUNGER 1 5 / 3 2 - 3 2 NS THREAD TO WITHIN .0 9 4 OF SHO ULDER LOCKNUT .62 ACROSS FLATS X .09 THICK 2 / g \

EPF8282

Contextual Info: EPF8282V Device Features ^ □ □ □ □ □ □ □ □ □ □ □ □ 3.3-V version of the EPF8282 device High-density, register-rich programmable logic device — 1,250 gates, 282 registers — 78 I /O pins and 4 dedicated inputs Fabricated on a 0.8-micron CMOS SRAM technology

epf8820a

Abstract: EPF8282A EPF8282AV EPF8452A EPF8636A EPC1064 EPC1213 EPC1441 EPF81188A EPF81500A
Contextual Info: FLEX 8000 Programmable Logic Device Family June 1999, ver. 10.01 Features. Data Sheet • ■ ■ ■ Table 1. FLEX 8000 Device Features Feature Usable gates EPF8282A EPF8452A EPF8282AV EPF8636A EPF8820A EPF81188A EPF81500A 2,500 4,000 6,000 8,000 12,000

8031 Intel Microprocessor

Abstract: 8048 intel microprocessor fuctional block diagram of telemetry siemens analog input modules
Contextual Info: PRELIMINARY • ■ ■ ■ : MX971 0 2 '■ ■ ; ISDN S/T CONTROLLER FEATURES • Pin-to-Pin and Register-to-Register compatible with Siemens 2186 • Full duplex 2B+D ISDN S/T Transceiver according to CCITT 1.430 • GCI digital interface • 3 types of 8-bit CPU interface

Contextual Info: CYPRESS CY7C09269V/79V/89V CY7C09369V/79V/89V PRELIMINARY 3.3V 16K/32K/64Kx 16/18 Synchronous Dual-Port Static RAM • High-speed clock to data access 7.5^1V9/12 ns max. • 3.3V Low operating power Features • True Dual-Ported mem ory cells which allow sim ulta­

Contextual Info: CYPRESS CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY 16K/32K/64K x16/18 Synchronous Dual Port Static RAM • Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location • Six Flow-Through/Pipelined devices

Contextual Info: fax id: 5211 CYPRESS PRELIMINARY CY7C09269V/79V/89V CY7C09369V/79V/89V 3.3V 16K/32K/64K x 16/18 Synchronous Dual-Port Static RAM Features • High-speed clock to data access 7.5/12 ns max. • 3.3V Low operating power • True Dual-Ported mem ory cells which allow sim ulta­

Contextual Info: fax id: 5217 ^CYPRESS CY7C09269/79/89 CY7C09369/79/89 PRELIMINARY 16K/32K/64K x16/18 Synchronous Dual Port Static RAM • Low operating power Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location • 6 Flow-Through/Pipelined devices

Contextual Info: FLEX 8000 Programmable Logic Device Family May 1999, ver. 10 Features. D a ta she et • ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers System-level features

HD XXXXX

Contextual Info: fax id: 5219 ^C YPR ESS CY7C09349 CY7C09359 PRELIMINARY 4K/8K x 18 Synchronous Dual-Port Static RAM • High-speed clock to data access 6.5/7.5/12 ns max. • Low operating power Features • True Dual-Ported mem ory cells which allow sim ulta­ neous access of the same mem ory location

Contextual Info: r- = CYPHhbo CY7C09349 PRELIMINARY_ CY7C09359 = 4K/8K x 18 Synchronous Dual-Port Static RAM High-speed clock to data access 6.5l1V7.5/9/12 ns max. Low operating power Features • True dual-ported m em ory cells which allow sim ulta­ neous access of the same m em ory location

Siemens k1403

Abstract: SKM 181 R siemens Package Outlines P-LCC Q67100-H6562 ic ZN 415 SBGX skm 191 siemens si 200 LC Communication cable pin diagram k1403 marking kjd
Contextual Info: S IE M E N S S /T Bus Interface C ircuit Extended 1 PEB 2081 Features • Full duplex 2B+D S/T-interface transceiver according to the following specifications: - ITU Recommendation 1.430 - ETS 300 012 - ANSI T 1.605 • 192 kbit/s transmission rate • Pseudo-ternary coding with 100 % pulse width

Contextual Info: LS211 ' * - I-Cube* 49 Port LAN Switching Element D escription Features • Single chip, Fast Ethernet switching fabric • Up to 100 M bit per-port switching capacity • Supports 49 full duplex ports • Four dedicated programmable output ports for M ulticast, port mirroring, or other port usage

ML7105-002

Contextual Info: FEDL7105-002-01 Issue Date: June. 10, 2013 ML7105-002 Bluetooth Low Energy •Overview ML7105-002 is a Bluetooth® Low Energy here in after LE LSI integrating RF, Baseband, microproccessor core and each peripherals, which has Bluetooth® LE compliant 2.4GHz band radio communication capability.

SIEMENS 3 TB 40 12 - 0A

Abstract: smd transistor 2T5 SIEMENS 3 TB 40 10 - 0A SIEMENS 3 TB 40 17 - 0A
Contextual Info: SIEMENS ISDN Subscriber Access Controller for UpN-lnterface Terminals ISAC -P TE PSB 2196 Preliminary Data 1 • • • • • • • • • • CMOS IC Features Cost/performance-optimized UPN-interface transceiver, compatible to PEB 2096 OCTAT-P HDLC-controller with 2 x 32 byte FIFO per direction

la 4620 ic smd

Abstract: mda 2060 peb pef moy SMD
Contextual Info: SIEM ENS PEB 2070 ISDN Communication Controller ICC CMOS 1C Preliminary Data 1 Features • Support of LAPD protocol • Different types of operating modes for increased flexibility • FIFO buffer (2x64 bytes) for efficient transfer of data packets • Serial interfaces:

manual repair offline ups 600 va

Abstract: schematic diagram online UPS online ups circuit schematic diagram 2549b neg ja8 PATH38 "Digital input board application guide" 500-002 offline ups circuit diagrams VMIVME 2534
Contextual Info: VMIVME-2534 32-BIT HIGH VOLTAGE DIGITAL INPUT OR OUTPUT BOARD WITH P2 I/O AND BUILT-IN-TEST INSTRUCTION MANUAL DOCUMENT NO. 500-002534-000 K Revised July 22, 1994 VME MICROSYSTEMS INTERNATIONAL CORPORATION 12090 SOUTH MEMORIAL PARKWAY HUNTSVILLE, ALABAMA 35803-3308

EPF8820

Contextual Info: Includes FLEX8000A FLE X 8000 OUUU Programmable Logic Device Family March 1995, ver. 6 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ Low-cost, high-density, register-rich CMOS programmable logic device family 2,500 to 16,000 usable gates 282 to 1,500 registers see Table 1

vhdl code for Clock divider for FPGA

Abstract: altera flex10k EPF10 speed grade
Contextual Info: FLEX 10K Embedded Programmable Logic Family J a n u a ry 1998, ver. 3 F e a tu re s . D ata S h e e t • ■ ■ The industry's first em bedded programmable logic device PLD family, providing system integration in a single device Em bedded array for implementing megafunctions, such as

8512A

Abstract: siemens cpu 224 wiring detail siemens b 58 295 la intel 80 C11E set up device
Contextual Info: SIEMENS ICs for Communications ISDN PC Adapter Circuit IPAC PSB 2115 Version 1.1 D a ta s h e e t 11.97 DS 1 PSB 2115 Revision History: Current Version: 11.97 Previous Version: Preliminary Data Sheet 03.97 Page in previous Version Page (in new Version) Subjects (major changes since last revision)

Contextual Info: FLEX 8000 Programmable Logic Device Family M a y 1 8 8 3 . ve r. 9.1 n Features. D a te S h e e t 888 SIS 888 88 Low-cost, high-density, register-rich CMOS programmable logic device PLD family (see Table 1) 2,500 to 16,000 usable gates 282 to 1,500 registers

D784038, 784038Y Sub-Series User’s Manual

Abstract: D784038
Contextual Info: MOS INTEGRATED CIRCUIT ¿1P D 7 8 4 0 3 5 , 7 8 4 0 3 6 , 7 8 4 0 3 7 , 7 8 4 0 3 8 16/8-BIT SINGLE-CHIP MICROCOMPUTER T h e /J P D 7 8 4 0 3 8 is a p ro d u c t o f th e ,u P D 7 8 4 0 3 8 s u b -s e r ie s in th e 7 8 K /IV s e rie s . It c o n ta in s v a rio u s p e rip h e ra l

HC4538

Abstract: ADC12062 ADC12062BIV ADC12062BIVF ADC12062CIV ADC12062CIVF ADC12062EVAL AN-450 jl-012
Contextual Info: S e m i c o n d u c t o r ADC12062 12-Bit, 1 MHz, 75 mW A /D Converter with Input Multiplexer and Sample/Hold General Description Features Using an innovative multistep conversion technique, the 12-bit ADC12062 CMOS analog-to-digital converter digitizes signals at a 1 MHz sampling rate while consuming a maxi­

Date Code Formats Altera EPF10K

Abstract: ep22v10 5962-9061102XA 5962-8854901xa 8686401LA 5962-8686401LA lift controller in vhdl ALTERA PART MARKING EPM7160 EPX780 transistor b2020
Contextual Info: Introduction Contents March 1995 Introduction The PLD Advantages of Altera