CI PAL 014 Search Results

Contextual Info: COM’L: -15/20 a MACH230-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 128 Macrocells ■ 128 Flip-flops; 4 clock choices ■ 15nstPD ■ 8 “PAL26V16” blocks with burled macrocells

Contextual Info: FINAL C O M 'L :-7 /1 0 /1 2 /1 5 IN D :-1 0 /1 2 /1 5 /2 0 MACH 5-320/M ACH 5LV-320 V A N A N A M D T I S C O M P A N Y M A C H 5 -3 2 0 /1 2 0 -7 /1 0 /1 2 /1 5 M A C H 5 -3 2 0 /1 9 2 - 7 /1 0 /1 2 /1 5 M A C H 5L V -320/18 4 - 7 /1 0 /1 2 /1 5 M A C H 5 -3 2 0 /1 6 0 - 7 /1 0 /1 2 /1 5

k019

Abstract: 14051 mach schematic MACH111SP MACH211SP mach131 DAPQ 11
Contextual Info: MACH 1 and 2 CPLD Families BEYOND PERFO R M A N CE High-Performance EE CMOS Programmable Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ ♦ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

Contextual Info: FINAL COM’L: -7.5/10/12/15/20 a Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • ■ ■ ■ ■ Programmable power-down mode 64 Outputs 64 Flip-flops; 4 clock choices

Contextual Info: MACH 1 and 2 CPLD Families BEYOND PERFORM ANCE H igh-Perform ance EE C M O S P rogram m able Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ — Programmable polarity — Registered or com binatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops

cd 208 PIR

Abstract: hp 3d6 AMD CPLD Mach 1 to 5 16x4 ram vhdl
Contextual Info: FINAL C O M 'L :-7 /1 0 /1 2 /1 5 IN D :-1 0 /1 2 /1 5 /2 0 M ACH 5-320/M ACH 5LV-320 S an amd company M A C H 5 -3 2 0 /1 2 0 -7 /1 0 /1 2 /1 5 M A C H 5 -3 2 0 /1 9 2 -7 /1 0 /1 2 /1 5 M A C H 5 L V -3 2 0 /1 8 4 -7 /1 0 /1 2 /1 5 M A C H 5 -3 2 0 /1 6 0 -7 /1 0 /1 2 /1 5

MACH130

Contextual Info: F IN A L COM’L: -15/20 IND: -18/24 MACH130-15/20 High-Density EE CMOS Programmable Logic a Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ ■ 4 “PAL26V16” Blocks

Contextual Info: PR ELIM IN A R Y C O M 'L :- 5 /7 /1 0 /1 2 I N D : -7 /1 0 /1 2 /1 5 M A C H 5 L V -1 2 8 BEYOND PERFORMANCE MACH5 LV-1 28/68-5/7/10/12 MACH5 LV-128/104-5/7/ 10/12 MACH5 LV-128/120-5/7/ 10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

Contextual Info: PRELIM INARY COM’L: -7/10/12/15/20 Z I Advanced Micro Devices M A C H 1 3 1 -7 / 1 0 / 1 2 / 1 5 /2 0 High-Density EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS • 84 Pins ■ 64 Outputs ■ 64 Macrocells ■ 64 Flip-flops; 4 clock choices ■ 7.5 ns tpo

transistor marking code E3t

Abstract: SAA7111 YUV411 a121 do ec nv RGB888 to CCIR656 317 jrc CCIR-656 PLCC68 QFP64 SAA7192
Contextual Info: Philips Semiconductors Preliminary specification Video Input Processor VIP SAA7111 CONTENTS 16.2.11 16.2.12 16.2.13 16.2.14 16.2.15 16.2.16 16.2.17 16.2.18 16.2.19 16.2.20 16.2.21 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA 5 ORDERING INFORMATION

Contextual Info: P R ELIM IN A R Y BEYOND PERFORMANCE C O M 'L : -5 /7 /1 0 /1 2 I N D : -7 /1 0 /1 2 /1 5 M A C H 5 LV -256 MACH5LV-256/68-5/7/10/12 MACH5LV-256/120-5/7/1 0/12 MACH5LV-256/104-5/7/10/12 MACH5 n/160-5/7/10/12 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

Contextual Info: FINAL COM'L:-7/10/12/15 IND:-10/12/15/20 MACH5-384/MACH5LV-384 V A A N IM A M D T I S C O M P A N Y M A C H 5 -3 84 /1 20-7/10/12/15 M A C H 5-384/192-7/10/12/15 M AC H5LV-384/184-7/10/12/15 M A C H 5-384/160-7/10/12/15 M A C H 5LV -384/120-7/10/12/15 M AC H5LV-384/192-7/10/12/15

Contextual Info: FIN AL C O M 'L : -7 /1 0 /1 2 /1 5 IN D : -1 0 /1 2 /1 5 /2 0 MACH5-256 V A N T I S COMP ANY MACH5-256/68-7/10/12/15 MACH5-256/120-7/10/12/1 5 MACH5-256/104-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Generation MACH Architecture DISTINCTIVE CHARACTERISTICS

1 - bit full adder multisim

Abstract: MACH4A
Contextual Info: MACH 4A Family BEYO N D PERFO RM A N CE High Performance EE CMOS Programmable Logic With Maximum Ease Of Use DISTINCTIVE CHARACTERISTICS Unique Features ♦ High-performance, EE CMOS 3.3-V CPLD Family ♦ First-Time-Fit and Good Refit ♦ High Speed — 5.5ns t PD Commercial and 7.5ns t PD Industrial

Contextual Info: CO M ’L: -5/7.5/10/12/15/20 M A C H 1 11 -5 /7 /1 0 /1 2 /1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Program m able power-down mode ■ 32 M acrocells ■ ■ 5 ns tpD ■ 32 Flip-flops; 4 clock choices

Contextual Info: FINAL BEYOND PERFORM ANCE COM’L: -10/12/15 IND: -12/14/18 M A C H 2 3 1 S P -1 0 /1 2 /1 5 High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ JTAG-Compatible, 5-V in-system programming

Contextual Info: cv V A N A I M A M D T FINAL C 0M 'L:-7/10/12/15 IND:-10/12/15/20 M A C H 5 -5 1 2 /M A C H 5 L V -5 1 2 I S C O M P A N Y MACH5-51 2/1 20-7/10/1 2/1 5 MACH5-512/192-7/10/12/15 MACH5-512/160-7/10/12/15 MACH5-512/256-7/10/12/15 MACH5-512/184-7/10/12/15 MACH5LV-512/120-7/10/12/15

GAL22CV10

Abstract: ark 3299 GAL22CV10-10
Contextual Info: October 1993 GAL22CV10-10 24-Pin Generic Array Logic Family Features Unique test circuitry and reprogrammable cells allow com­ plete AC, DC, cell, and functionality testing during manufac­ ture. Therefore, NSC guarantees 100% field programmabili­ ty and functionality of NSC GAL devices. In addition, a

AIT1168

Abstract: schematic diagram vga to tv composite to vga converter ic AIT1108 vga to pal video convertor ic schematic diagram vga to svideo schematic diagram vga to composite vga to tv converter ic ic Composite Video to VGA schematic diagram scart to vga
Contextual Info: VSPro – Video Signal Processor AIT1168 Video Signal Processor VSPro ™ Product Information US Patent 5526055 ♦ VGA to NTSC/PAL Converter ♦ The AIT1168 Video Signal Processor converts the analog RGB output signals from any VGA compatible graphic signal into analog NTSC or

KXO 97 marking

Abstract: 1006sa KXO - 97 marking CP 6, WIMO
Contextual Info: FINAL C O M 'L:-7/10/12/15 IN D :-10/12/15/20 MACH5-256 V a n A N a m d T I S c o m p a n y MACH5-256/68-7/10/12/15 MACH5-256/104-7/10/12/15 MACH5-256/120-7/10/12/15 MACH5-256/160-7/10/12/15 Fifth Gener3tion MAGH Architecture DISTINCTIVE CHARACTERISTICS

Contextual Info: COM’L: -15/20, Q-25 MACH435-15/20, Q-25 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 84 Pins in PLCC ■ Up to 20 product terms per function, with XOR ■ 128 Macrocells ■ Flexible clocking ■ l5nstpD

Contextual Info: COM’L: -15/20 & MACH445-15/20 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 100-pin version of the MACH435 in PQFP Up to 20 product terms per function, with XOR ■ 5 V, In-circuit programmable Flexible clocking

Contextual Info: FINAL C O M 'L :-7 /1 0 /1 2 /1 5 IN D :-1 0 /1 2 /1 5 /2 0 MACH 5-320/M ACH 5LV-320 V A N A N A M D T I S C O M P A N Y MACH5-320/120-7/10/12/1 5 MACH5-320/192-7/10/12/15 MACH5LV-320/184-7/10/12/15 MACH5-320/160-7/10/12/15 MACH5LV-320/120-7/10/12/15 MACH5LV-320/192-7/10/12/15

vp07

Abstract: vp08 TI CCIR-656 F111 LQFP64 PLCC68 QFP64 SAA7111 SAA7111A SAA7111AWP
Contextual Info: Philips Semiconductors Preliminary specification SAA7111A Enhanced Video Input Processor EVIP CONTENTS 1 FEATURES 2 APPLICATIONS 3 GENERAL DESCRIPTION 4 QUICK REFERENCE DATA ORDERING INFORMATION BLOCK DIAGRAM PINNING 8 FUNCTIONAL DESCRIPTION 8.1 Analog input processing