ACH211 Search Results

Contextual Info: CO M ’L: -5/7.5/10/12/15/20 M A C H 1 11 -5 /7 /1 0 /1 2 /1 5 /2 0 High-Density EE CMOS Programmable Logic Advanced Micro Devices DISTINCTIVE CHARACTERISTICS • 44 Pins ■ Program m able power-down mode ■ 32 M acrocells ■ ■ 5 ns tpD ■ 32 Flip-flops; 4 clock choices

Contextual Info: FINAL COM’L : -7/10/12/15 IN D :-10/12/14/18 MACH 4-64/MACH4LV-64 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 pins in PLCC, 44 and 48 pins in TQFP

k019

Abstract: 14051 mach schematic MACH111SP MACH211SP mach131 DAPQ 11
Contextual Info: MACH 1 and 2 CPLD Families BEYOND PERFO R M A N CE High-Performance EE CMOS Programmable Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ ♦ High-performance electrically-erasable CMOS PLD families 32 to 128 macrocells 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages

bpi400

Abstract: teradyne flex tester tms 3755 FLEX-700 LA 7522 machpro 1,1 teradyne lasar HP3070 MACH211SP PALCE22V10
Contextual Info: FINAL COM’L: -6/7/10/12/15 IND: -10/12/14/18 M A C H 2 1 1 S P -6 /7 /1 0 /1 2 /1 5 B E Y O N D P E R FO R M A N C E High-Performance EE CMOS In-System Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ JTAG-Compatible, 5-V in-system programming

Contextual Info: FINAL " V A N N A M D I N D : - 1 0 /1 2 /1 4 /1 8 M A C H 2 1 1 S P -7 /1 0 /1 2 /1 5 V A C O M 'L : - 7 /1 0 /1 2 /1 5 T I S High-Performance EE CMOS In-System Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦

Contextual Info: MACH 1 and 2 Families AN A M D C O M P A N Y High-Performance, Low Cost EE CMOS Programmable Logic DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ High-performance, low-cost, electrically-erasable CMOS PLD families 32 to 128 macrocells 1250 to 5000 PLD gates

Contextual Info: MACH 1 and 2 CPLD Families BEYOND PERFORM ANCE H igh-Perform ance EE C M O S P rogram m able Logic FEATURES ♦ ♦ ♦ ♦ ♦ ♦ — Programmable polarity — Registered or com binatorial outputs — Internal and I/O feedback paths — D-type or T-type flip-flops

Contextual Info: MACH 1 and 2 CPLD Families BEY O N D PER FO RM AN C E High-Performance EE CMOS Programmable Logic FEATURES — — — — — — — Programmable polarity Registered or com binatorial outputs Internal and I/O feedback paths D-type or T-type flip-flops O utput Enables

Contextual Info: FINAL C O M 'L : - 7 /1 0 /1 2 /1 5 IN D : -1 0 /1 2 /1 4 /1 8 M A C H 2 1 1 -7 /1 0 /1 2 /1 5 V A N A N A M D T I S High-Performance EE CMOS Programmable Logic C O M P A N Y DISTINCTIVE CHARACTERISTICS ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ ♦ 44 Pins in PLCC and TQFP