CDCM1802RGTR Search Results
CDCM1802RGTR Result Highlights (1)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
|---|---|---|---|---|---|
| CDCM1802RGTR | Texas Instruments | Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-VQFN -40 to 85 |
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CDCM1802RGTR Datasheets (6)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CDCM1802RGTR | Texas Instruments | CDCM1802 - Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85 | Original | 553.19KB | 25 | ||
| CDCM1802RGTR | Texas Instruments | Logic and Timing, Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output, Tape and Reel | Original | 586.1KB | 20 | ||
| CDCM1802RGTR | Texas Instruments | Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85 | Original | 833.74KB | 24 | ||
| CDCM1802RGTRG4 | Texas Instruments | CDCM1802 - Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85 | Original | 553.19KB | 25 | ||
| CDCM1802RGTRG4 | Texas Instruments | Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output | Original | 810.79KB | 23 | ||
| CDCM1802RGTRG4 | Texas Instruments | Clock Buffer w/Programmable Divider, LVPECL I/O + addl LVCMOS output 16-QFN -40 to 85 | Original | 833.74KB | 24 |
CDCM1802RGTR Price and Stock
Texas Instruments CDCM1802RGTRClock Divider/Fanout Buffer 2-OUT 1-IN 1:2 16-Pin VQFN EP T/R |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CDCM1802RGTR | 1,425 | 37 |
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CDCM1802RGTR | 140 | 1 |
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CDCM1802RGTR | 112 |
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CDCM1802RGTR | 1,425 | 1 |
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Buy Now | ||||||
Texas Instruments CDCM1802RGTRG4Low Skew Clock Driver, 1802 Series, 2 True Output(s), 0 Inverted Output(s), PQCC16 |
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| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CDCM1802RGTRG4 | 9,049 |
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CDCM1802RGTR Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
SLUA271
Abstract: QFN PACKAGE thermal resistance JESD51-7 QFN PACKAGE Junction to PCB thermal resistance CDCM1802 CDCM1802RGTR SCAA062 SLUA
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Original |
cdcm1802scas759800-mhz200-mhz+7 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 |
Original |
cdcm1802scas759a800-mhz200-mhz+1 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+2 | |
SLUA271
Abstract: CDCM1802 CDCM1802RGTR SCAA062
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Original |
cdcm1802scas759800-mhz200-mhz+3 | |
SLUA271
Abstract: SCAA062 CDCM1802 CDCM1802RGTR
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Original |
cdcm1802scas759800-mhz200-mhz+3 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
CDCM1802
Abstract: CDCM1802RGTR SCAA062 SLUA271
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Original |
cdcm1802scas759800-mhz200-mhz+3 | |
CDCM1802
Abstract: CDCM1802RGTR SCAA062 SLUA271
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Original |
cdcm1802scas759800-mhz200-mhz+3 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
|
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
|
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 |
Original |
cdcm1802scas759a800-mhz200-mhz+1 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
SLUA271Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+5 | |
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Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759 − APRIL 2004 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 D 1 Vss D D VDDPECL |
Original |
cdcm1802scas759800-mhz200-mhz+1 | |
|
Contextual Info: CDCM1802 CLOCK BUFFER WITH PROGRAMMABLE DIVIDER, LVPECL I/O + ADDITIONAL LVCMOS OUTPUT SCAS759A − APRIL 2004 − JULY 2009 D Distributes One Differential Clock Input to EN S1 Vss S0 16 15 14 13 11 Y0 IN 3 10 Y0 VBB 4 9 VDD0 8 2 Vdd1 IN 7 VDD0 Y1 D D 12 6 |
Original |
cdcm1802scas759a800-mhz200-mhz | |