CCOGN Search Results

MAX9217

Abstract: MAX9247 MAX9248 MAX9250
Contextual Info: 19-3943; Rev 3; 4/09 KIT ATION EVALU LE B A IL A AV 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

ax 2008 lqfp 48

Abstract: MAX9217 MAX9247 MAX9248 MAX9250 MAX9250ECM
Contextual Info: 19-3943; Rev 2; 5/08 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

TMS3401

Abstract: SPVU001 MD653 SPVU001B ls 010s 100s MS3401
Contextual Info: TM S3 4 0 1 0 GRAPHICS SY ST EM PROCESSOR SPVS002C • • • TOP VIEW 1 3 2 ns . . ( T M S 3 4 0 1 0 6 0 ) 1 6 0 ns . . ( T M S 3 4 0 1 0 - 5 0 ) 2 0 0 ns . (T M S 3 4 0 1 0 -4 0 ) Fully P rog ra m m a b le 32 -B it General-Purpose P roc e ss or w i t h 1 2 8 - M e g a b Y tc A d d re s s

MC10800

Abstract: MC10802 MC10803 MECL 10000 input threshold MC10801 141S M10800 MECL/LSI processor MSI MS-5 MS10 MS11
Contextual Info: MOTOROLA MECL — LSI MEMORY INTERFACE FUNCTION INTRO DUCTIO N The M C10803 M em ory Interface Function is an L S I building block for interfacing a high speed processor system to main m em ory or peripheral equipm ent. The circuit contains the logic and storage

Contextual Info: 19-3943; Rev 1; 8/06 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

221A-06

Abstract: 221D-02 MPPD2021 mla1n06cl ccogn
Contextual Info: V T M O S CASE 221D-02 ISOLATED TO-220 MLA PREFIX (MPPD PREFIX) S T0-220AB CASE 221A-06 (MLP PREFIX) The SMARTDISCRETE Concept MLA1N06CL and MLP1N06CL From a stan dard po w e r M O S F E T pro cess, several active and passive elem e nts can be o b tain ed tha t provide on-chip

MAX9217

Abstract: MAX9247 MAX9248 MAX9250 MAX9250ECM MAX9250ETM 3248L
Contextual Info: 19-3943; Rev 0; 1/06 27-Bit, 2.5MHz-to-42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Z30V

Contextual Info: 1. M e c h a n ic a l D im e n sio n s: 2. S c h e m a t i c : Sec Pri -o 5 1 o A 1 .6 5 XFMRS 1 .3 5 M ax -o 6 r~n YYWW -O 7 o- -O B o XF—4 - 1 6 TO X155D 1 TTTir F1 0 .2 5 0 ^ 1 M ax iE 0 .8 5 0 i 3. E l e c t r i c a l G S p e c ific a tio n s : Prim ory: Pins 1 - 4

Contextual Info: 19-3943; Rev 3; 4/09 KIT ATION EVALU LE B A IL A AV 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is

MAX9248

Abstract: MAX9217 MAX9247 MAX9250
Contextual Info: 19-3943; Rev 3; 4/09 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is converted to 18 bits of parallel video data and in the control phase, the input is converted to 9 bits of parallel control data. The separate video and control phases take

Contextual Info: EVALUATION KIT AVAILABLE MAX9248/MAX9250 27-Bit, 2.5MHz to 42MHz DC-Balanced LVDS Deserializers General Description The MAX9248/MAX9250 digital video serial-to-parallel converters deserialize a total of 27 bits during data and control phases. In the data phase, the LVDS serial input is