CAPACITANCE IN BGA PACKAGE Search Results

AN1001

Abstract: application notes capacitor cross reference active and passive electronic components capacitance in BGA package capacitor package resistor resistor 220 ohm resistor 220 resistor cross reference
Contextual Info: Application Note AN1001 ClearONE RC BGA Configuration Options Introduction The double-sided construction of the CTS ceramic Ball Grid Array BGA package allows the PC board designer to closely locate passive resistor and capacitor elements near the active signal sources and

C4 to BGA

Abstract: MX23L1612 MX23L1612XI-70 MX23L1612XI-70G MX23L1612XI-90 MX23L1612XI-90G PM0815
Contextual Info: MX23L1612 16M-BIT MASK ROM PIN DESCRIPTION FEATURES • Bit organization - 2M x 8 byte mode - 1M x 16 (word mode) • Fast access time - Random access:70ns(max.) • Current - Operating:25mA - Standby:5uA • Supply voltage - 2.7V ~ 3.6V • Package - 48 ball mini BGA (6mm x 8mm, ball pitch 0.8mm, ball

Turn-Key

Abstract: Adapters Sockets Product Presentations Giga-snaP™ BGA SMT Adapters Receptacles Prototyping Adapters Surface Mount Package Emulation Probing and Analysis Adapters BGA Sockets
Contextual Info:  RoHS ISO w i t h 900 d 08 20 i g n : 1 es Certified Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . . . 2 Catalog 26 Receptacles . . . . . . . . . . . . . . . . . . . . . 22 Package Conversion For Production Applications . . . . 24-25

GS8342Q10BD-357

Abstract: GS8342Q37BD-200I 8342Q07101937B
Contextual Info: GS8342Q07/10/19/37BD-357/333/300/250/200 36Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

GS8342DT10BGD-350I

Abstract: IR receiver TK 19 205
Contextual Info: GS8342DT07/10/19/37BD-450/400/350/333/300 36Mb SigmaQuad-II+TM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

Contextual Info: Preliminary GS8342QT07/10/19/37BD-357/333/300/250/200 36Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS8342D19BGD-300

Abstract: GS8342D10BD-350I GS8342D19BD-350I 8342D07101937B
Contextual Info: GS8342D07/10/19/37BD-450/400/350/333/300 36Mb SigmaQuad-II+TM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

GS8662DT19BD-400

Contextual Info: GS8662DT07/10/19/37BD-450/400/350/333/300 72Mb SigmaQuad-II+TM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 Clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

MX23L8102

Abstract: MX23L8102XI-12 MX23L8102XI-70 MX23L8102XI-90
Contextual Info: MX23L8102 8M-BIT MASK ROM FEATURES PIN DESCRIPTION • Bit organization - 1M x 8 byte mode - 512K x 16 (word mode) • Fast access time - Random access:70ns(max.) • Current - Operating:15mA - Standby:5uA • Supply voltage - 2.7V ~ 3.6V • Package - 48 ball mini BGA (6mm x 8mm, ball pitch 0.8mm, ball

top 48 C1

Abstract: TSOP 86 Package MX23L8103 MX23L8103TC-12 MX23L8103TC-70 MX23L8103TC-90 MX23L8103TI-12 MX23L8103TI-70 MX23L8103TI-90 commercial grade item
Contextual Info: MX23L8103 8M-BIT MASK ROM FEATURES PIN DESCRIPTION • Bit organization - 1M x 8 byte mode - 512K x 16 (word mode) • Fast access time - Random access:70ns(max.) • Current - Operating:15mA - Standby:5uA • Supply voltage - 2.7V ~ 3.6V • Package - 48 pin TSOP(12mm x 20mm)

Contextual Info: Preliminary GS73024AB BGA Commercial Temp Industrial Temp 128K x 24 3Mb Asynchronous SRAM Features 8, 10, 12 ns 3.3 V VDD 119-Bump Ball Grid Array Package • Fast access time: 8, 10, 12 ns • CMOS low power operation: 250/200/170 mA at minimum cycle time

Contextual Info: Preliminary GS82582QT06/11/20/38E-500/450/400/375 288Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS82582Q06/11/20/38E-500/450/400/375 288Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: GS81302Q07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

GS81302QT19GE-200

Contextual Info: GS81302QT07/10/19/37E-333/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 333 MHz–200 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

48 ball VFBGA

Abstract: 90 ball VFBGA LVTH162 micro pitch BGA tSSOP 56 socket TSSOP YAMAICHI SOCKET 48-PIN 56-PIN ALVCH16373 LVCH16244A
Contextual Info: Application Report SZZA029B - May 2002 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch, Very Thin Fine-Pitch BGA VFBGA Packages Frank Mortan and Mark Frimann Standard Linear & Logic ABSTRACT TI’s 56-ball MicroStar Jr. package, registered under JEDEC MO-225, has demonstrated

GS81302QT07E-300

Contextual Info: GS81302QT07/10/19/37E-318/300/250/200 144Mb SigmaQuad-II+TM Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.0 clock Latency • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface

MX23L8103

Abstract: MX23L8103TC-12 MX23L8103TC-70 MX23L8103TC-90 MX23L8103TI-12 MX23L8103TI-70 MX23L8103TI-90 TSOP 48 PIN
Contextual Info: MX23L8103 8M-BIT MASK ROM FEATURES PIN DESCRIPTION • Bit organization - 1M x 8 byte mode - 512K x 16 (word mode) • Fast access time - Random access:70ns(max.) • Current - Operating:15mA - Standby:5uA • Supply voltage - 2.7V ~ 3.6V • Package - 48 pin TSOP(12mm x 20mm)

GS8182D

Contextual Info: GS8182D08/09/18/36BD-400/375/333/300/250/200/167 18Mb SigmaQuad-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 400 MHz–167 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

GS81302D36E-250

Contextual Info: Preliminary GS81302D08/09/18/36E-375/350/333/300/250 144Mb SigmaQuadTM-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342D08/09/18/36BD-400/350/333/300/250 400 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O 36Mb SigmaQuad-IITM Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package

Contextual Info: GS81302T08/09/18/36E-375/350/333/300/250 144Mb SigmaDDRTM-II Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaDDR Interface • Common I/O bus • JEDEC-standard pinout and package

Contextual Info: Preliminary GS8342TT06/11/20/38BD-550/500/450/400/350 36Mb SigmaDDRTM-II+ Burst of 2 SRAM 165-Bump BGA Commercial Temp Industrial Temp Features • 2.5 Clock Latency • Simultaneous Read and Write SigmaDDRTM Interface • JEDEC-standard pinout and package

GS81302D36E-250

Contextual Info: GS81302D08/09/18/36E-375/350/333/300/250 144Mb SigmaQuadTM-II Burst of 4 SRAM 165-Bump BGA Commercial Temp Industrial Temp 375 MHz–250 MHz 1.8 V VDD 1.8 V and 1.5 V I/O Features • Simultaneous Read and Write SigmaQuad Interface • JEDEC-standard pinout and package