CABGA 56 Search Results

GR-1244

Abstract: GR-253 ZL30106 ZL30116 ZL30117 ZL30119
Contextual Info: ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet June 2008 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30116GGGV2 100 Pin CABGA ZL30116GGG2V2100 Pin CABGA*

GR-1244

Abstract: GR-253 ZL30106 ZL30116 ZL30116GGG ZL30116GGG2 ZL30117 ZL30119 wand
Contextual Info: ZL30116 SONET/SDH Low Jitter System Synchronizer Data Sheet December 2005 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30116GGG 100 Pin CABGA Trays ZL30116GGG2 100 Pin CABGA* Trays

GR-253-CORE

Abstract: STM-16 ZL30123 ZL30123GGG ZL30123GGG2 "network interface cards"
Contextual Info: ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA*

GR-253-CORE

Abstract: ZL30119 ZL30119GGG ZL30119GGG2 "network interface cards"
Contextual Info: ZL30119 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet December 2005 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30119GGG 100 Pin CABGA Trays ZL30119GGG2 100 Pin CABGA*

ZL30123

Abstract: GR-253-CORE STM-16 ZL30123GGG ZL30123GGG2 "network interface cards"
Contextual Info: ZL30123 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30123GGG 100 Pin CABGA Trays ZL30123GGG2 100 Pin CABGA*

pal22v10h

Abstract: MM74HC245AWM 96F8740 PCC473BCTND MC68340 PM4314 PM4388 PM6344 PM7364 PM7375
Contextual Info: PM4388 TOCTL PRELIMINARY INFORMATION REFERENCE DESIGN PMC-980942 ISSUE 1 CABGA TOCTL WITH FREEDM-32 REFERENCE DESIGN PM4388 CABGA TOCTL WITH FREEDM-32 REFERENCE DESIGN PRELIMINARY INFORMATION ISSUE 1: SEPT 1998 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE

ZL30155GGG2

Abstract: ZL30155 ZL30155GGG zl3015
Contextual Info: ZL30155 Dual Channel Universal Clock Translator Short Form Data Sheet January 2011 Features Ordering Information • Two independent clock channels • Programmable synthesizers generate any clockrate from 1 kHz to 720 MHz ZL30155GGG 100 Pin CABGA ZL30155GGG2 100 Pin CABGA*

GR-253-CORE

Abstract: ZL30117 ZL30117GGG ZL30117GGG2 "network interface cards"
Contextual Info: ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA*

GR-1244-CORE

Abstract: ZL30120 ZL30120GGG ZL30120GGG2 "network interface cards"
Contextual Info: ZL30120 SONET/SDH/Ethernet Multi-Rate Line Card Synchronizer Data Sheet May 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30120GGG 100 Pin CABGA Trays ZL30120GGG2 100 Pin CABGA* Trays

GR-253-CORE

Abstract: ZL30119 ZL30119GGG ZL30119GGG2 "network interface cards"
Contextual Info: ZL30119 SONET/SDH OC-48/OC-192 Line Card Synchronizer Data Sheet June 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30119GGG 100 Pin CABGA Trays ZL30119GGG2 100 Pin CABGA*

PACKAGE DIMENSIONS

Contextual Info: Package Diagrams Index of Package Diagrams 100-Ball caBGA Package . 12 120-Pin PQFP Package . 12 128-Pin PQFP Package . 13 128-Pin TQFP Package . 13

ZL30155GGG

Abstract: ZL30155GGG2 ZL30155 CABGA hz28
Contextual Info: ZL30155 Dual Channel Universal Clock Translator Short Form Data Sheet April 2010 A full Data Sheet is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30155GGG ZL30155GGG2 Features 100 Pin CABGA

sumitomo g760

Abstract: sumitomo EME G760 SUMITOMO EME G770 IDT75N43102S50BCG KMC-3580 EME-G770 IDT75N414S125BC IDT70T653MS12BCG JESD22-B116 IDT75N43102S62BCG
Contextual Info: Integrated Device Technology, Inc. 6024 Silver Creek Valley Road, Dan Jose, CA 95138 PRODUCT/PROCESS CHANGE NOTICE PCN PCN #: A-0607-05 DATE: 25-Aug-06 Product Affected: CABGA-256 17x17mm, CVBGA-52/56 4.5X7.0mm, FPBGA-96 5.5x13.5mm, FPBGA-208 15x15mm, PBGA-119

ZL30160GGG2

Abstract: zl30160 ZL30160GGG transponders philips
Contextual Info: ZL30160 Four Channel Universal Clock Translator Short Form Data Sheet April 2010 A full Data Sheet is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30160GGG ZL30160GGG2 100 Pin CABGA

ZL30116GGG

Abstract: ZL30116GGG2 ZL30117 ZL30119 GR-1244 GR-253 ZL30106 ZL30116
Contextual Info: ZL30116 SONET/SDH OC-48/OC-192 System Synchronizer Data Sheet June 2006 A full Design Manual is available to qualified customers. To register, please send an email to TimingandSync@Zarlink.com. Ordering Information ZL30116GGG ZL30116GGG2 Features • 100 Pin CABGA

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.2, September 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Abstract: LCMXO2-2000 pinout
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

LCMXO2-256 pinout

Contextual Info: MachXO2 Family Data Sheet Preliminary DS1035 Version 01.2, April 2011 MachXO2 Family Data Sheet Introduction April 2011 Features Preliminary Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O 

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 2.5, May 2014 MachXO2 Family Data Sheet Introduction February 2014 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: ECP5 Family Data Sheet Advance DS1044 Version 1.1, June 2014 ECP5 Family Data Sheet Introduction March 2014 Advance Data Sheet DS1044 Features  Higher Logic Density for Increased System Integration  Pre-Engineered Source Synchronous I/O • • •

MACHXO2 7000 pinout

Abstract: MachXO2-4000
Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.3, December 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.1, June 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only

lcmxo2-1200

Abstract: LCMXO2-2000 LCMXO2-256 LCMXO2-4000 LCMXO2-640 LCMXO2-256HC-4TG100I LCMXO2-7000 MACHXO2 7000 pinout file MachXO2-1200 LCMXO2-2000HC-4BG256C
Contextual Info: MachXO2 Family Data Sheet Advance DS1035 Version 01.0, November 2010 MachXO2 Family Data Sheet Introduction November 2010 Features Advance Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks per edge for high-speed 

Contextual Info: MachXO2 Family Data Sheet DS1035 Version 02.0, January 2013 MachXO2 Family Data Sheet Introduction January 2013 Features Data Sheet DS1035  Flexible On-Chip Clocking • Eight primary clocks • Up to two edge clocks for high-speed I/O  interfaces top and bottom sides only