C199S Search Results

4lc2m8

Contextual Info: MT4LC2M8E7 S 2 MEG X 8 DRAM ÍMICnON :fl TtCHWXOGV.WC. 2 MEG x 8 DRAM DRAM 3.3V, EDO PAGE MODE, OPTIONAL SELF REFRESH FEATURES • Industry-standard x8 pinout, timing functions and packages • High-performance C M O S silicon-gale process • Single +3.3V ±0.3V pow er supply

Contextual Info: PRELIMINARY M MTt8LD T 47Z(X}(SJI 4 MEG xTZDETAWI M O D ULE IC R O N • u n w a- g rr n l 4 MEG x 72 DRAM MODULE 32 MEGABYTE, ECC, 3.3V, OPTIONAL SELF REFRESH, FAST PAGE OR EDO PAGE MODE MATURES ’ JED EC - and industry-standard E C C pinout in a 168-pin, dual-in-line memory module (D IM M )

Contextual Info: ADVANCE M • ir S D N MT4 LD T 164 B(N ), MT8LD264 B(N ), MT16LD464 B(N ) 1 ,2 ,4 M EG X 64 B U R S T EDO DRAM M O D U LES BURST EDO DRAM MODULE 1, 2, 4 MEG X 64 8, 16, 32 MEGABYTE, 3.3V, BURST EDO FEATURES PIN ASSIGNMENT (Front View) 168-Pin DIMM • 168-pin, dual-in-line memory module (D IM M )

T9049

Abstract: A7005 MT9D49M-6
Contextual Info: » M I C-n Rw On Ni I iH M 49 4 MEGX 9 DRAMM OT9D DULE DRAM MODULE 4 MEG X 9 DRAM FAST PAGE MODE FEATURES OPTIONS MARKING • Timing 60ns access 70ns access 80ns access -6 -7 -8 Packages Leadless 30-pin SIMM M Part Number Example: MT9D49M-6 PIN ASSIGNMENT Top View

Contextual Info: ADVANCE MT41 LC256K32D4 S 256K x 32 SGRAM MICRON I TECHNOLOGY. MC. 256K X 32 SGRAM PULSED RAS, DUAL BANK, PIPELINED, 3.3V OPERATION FEATURES • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be

mi6c3

Contextual Info: PRELIMINARY M IC R O N K ' MT4LG1M16C3 L/S t MEG X 16 DRAW! T B W C L O S r. N C D R A M 1 M E G x 1 6 D R A M 3.3V, FAST PAGE MODE, OPTIONAL EXTENDED OR SELF REFRESH FEATURES PTIONS MARKING Tim ing 60ns access 70ns access -6 -7 Refresh Rate Standard 16m s period

T41C

Abstract: T41C-4M
Contextual Info: PRELIMINARY H/rT4LC4M4Gtff S M BK jc* BURST EDO DRAWT BURST EDO DRAM FEATURES • Burst order, interleave or linear, programmed by executing WCBR cycle after initialization • Single power supply: +3.3V ±5% • All inputs and outputs are LVTTL compatible with 5V

Contextual Info: PRELIMINARY jMi r a n ^ r fc wnr4LC2M8FtZMEGxSBURST" EDQDRAR/T BURST EDO DRAM 2 MEG x 8 FEATURES PIN ASSIGNMENT Top View • Burst order, interleave or linear, programmed by executing WCBR cycle after initialization • Single power supply: +3.3V *5% • All inputs and outputs are LVTTL compatible with 5V