BWC 110 TRANSISTOR Search Results

CY7C1347D-200AC

Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC CY7C1347D
Contextual Info: CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features Functional Description • Fast access times: 2.5 and 3.5 ns This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell

CY7C1347D

Abstract: CY7C1347D-200AC CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC 4N70
Contextual Info: CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features Functional Description • Fast access times: 2.5 and 3.5 ns This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell

Contextual Info: CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features Functional Description • Fast access times: 2.5 and 3.5 ns This Cypress Synchronous Burst SRAM employs high-speed, low-power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell

CY7C1347D

Abstract: CY7C1347D-225BGC CY7C1347D-250AC CY7C1347D-250BGC
Contextual Info: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time

CY7C1347D-250BGC

Abstract: CY7C1347D CY7C1347D-225BGC CY7C1347D-250AC
Contextual Info: 327 CY7C1347D 128K x 36 Synchronous-Pipelined Cache SRAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz 1.5 ns set-up time and 0.5 ns hold time

4918A

Abstract: CY7C1327C GVT71256DA18
Contextual Info: CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 256K x 18/128K x 36 Synchronous-Pipelined Cache RAM Features • • • • • • • • • • • • • • • • • • • Fast access times: 2.5 and 3.5 ns Fast clock speed: 250, 225, 200, and 166 MHz

GVT71128DA36

Abstract: GVT71256DA18
Contextual Info: ADVANCE INFORMATION GALVANTECH, INC. GVT71128DA36/GVT71256DA18 128K X 36/256K X 18 SYNCHRONOUS SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT 128K x 36 SRAM 256K x 18 SRAM +3.3V SUPPLY, FULLY REGISTERED FEATURES GENERAL DESCRIPTION • • • • • The Galvantech Synchronous Burst SRAM family

GVT71256D36

Abstract: GVT71512D18 3G MARKING
Contextual Info: GALVANTECH, INC. GVT71256D36/GVT71512D18 256K X 36/512K X 18 SYNCHRONOUS SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT FEATURES • • • • • • • • • • • • • • • • • • Fast access times: 2.5ns, 3.0ns, and 3.5ns Fast clock speed: 225, 200, 166, and 150MHz

GVT71256C36

Abstract: GVT71512C18 4h35
Contextual Info: GALVANTECH, INC. GVT71256C36/GVT71512C18 256K X 36/512K X 18 SYNCHRONOUS SRAM SYNCHRONOUS BURST SRAM PIPELINED OUTPUT FEATURES • • • • • • • • • • • • • • • • • • Fast access times: 2.5ns, 3.0ns, and 3.5ns Fast clock speed: 225, 200, 166, and 150MHz

100-PIN

Abstract: GVT71256ZC36 GVT71512ZC18
Contextual Info: PRELIMINARY GVT71256ZC36/GVT71512ZC18 256K X 36/512K X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT FEATURES • • • • • • • • • • • • • • • Zero Bus Latency, no dead cycles between write and read cycles Fast clock speed: 200, 166, 133, and 100MHz

100-PIN

Abstract: GVT71256ZB36 GVT71512ZB18 4g81
Contextual Info: PRELIMINARY GVT71256ZB36/GVT71512ZB18 256K X 36/512K X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS 256K x 36 SRAM ZBL SRAM 512K x 18 SRAM FLOW-THRU OUTPUT +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES • • • • • • • • • • • • • • • Zero Bus Latency, no dead cycles between write and read

CY7C1360A1-150AC

Abstract: CY7C1362A1 GVT71512DA18
Contextual Info: CY7C1360A1/GVT71256DA36 CY7C1362A1/GVT71512DA18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM eral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

GVT71256D36B-5

Abstract: CY7C1362A GVT71512D18 7c136
Contextual Info: 1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

100-PIN

Abstract: GVT71256ZC36 GVT71512ZC18
Contextual Info: ADVANCE INFORMATION GVT71512ZC36/GVT71A24ZC18 512K X 36/1M X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT 512K x 36 SRAM 1M x 18 SRAM +3.3V SUPPLY, +3.3V or +2.5V I/O FEATURES GENERAL DESCRIPTION • The GVT71512ZC36 and GVT71A24ZC18 SRAMs are

Contextual Info: CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1367A

Abstract: GVT71512C18
Contextual Info: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Pipelined SRAM Features and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous

CY7C1367A

Abstract: GVT71512C18 CY7C1367A-166AC 6n35
Contextual Info: CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining

CY7C1363A

Abstract: GVT71256B36 GVT71512B18
Contextual Info: CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

marking 3U 3T 3C diode 3E 3G

Abstract: GVT71256B36 GVT71512B18
Contextual Info: GALVANTECH, INC. GVT71256B36/GVT71512B18 256K X 36/512K X 18 SYNCHRONOUS SRAM SYNCHRONOUS BURST SRAM FLOW-THROUGH FEATURES • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz

GALVANTECH ZBL

Abstract: CY7C1354A CY7C1356A
Contextual Info: CY7C1354A CY7C1356A 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns • Internally synchronized registered outputs eliminate

CY7C1363A

Abstract: GVT71256B36 GVT71512B18 GVT71512B18TA-8
Contextual Info: 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

GVT71256B36T-7

Abstract: CY7C1363A GVT71256B36 GVT71512B18 926B1 a453t GVT71256B36TA
Contextual Info: 1CY7C1361A CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 256K x 36/512K x 18 Synchronous Burst Flowthrough SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip

CY7C1356A

Abstract: GVT71512ZC18
Contextual Info: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency™, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns

100-PIN

Contextual Info: PRELIMINARY GVT75256ZC36/GVT75512ZC18 256K X 36/512K X 18 ZBL SRAM GALVANTECH, INC. SYNCHRONOUS ZBL SRAM PIPELINED OUTPUT FEATURES • • • • • • • • • • • • • • • Zero Bus Latency, no dead cycles between write and read cycles Fast clock speed: 150, 133, and 100MHz