BURST MODEM Search Results

BCM3140

Abstract: BCM3040 BCM3214 Ingress Cancellation qam modulator docsis ti
Contextual Info: BCM3140 DUAL UNIVERSAL ADVANCED TDMA/SCDMA PHY-LAYER BURST RECEIVER FEATURES SUMMARY OF BENEFITS • The BCM3140 is a universal headend advanced TDMA and • Presents a high-performance, integrated solution for SCDMA physical layer QPSK/QAM burst receiver.

EP3003

Abstract: CDRH4D18 CR43 D312C common-drain
Contextual Info: EP3003 Revision History Revision 0.1 Apr. 2006 - First release. Revision 0.2 (Feb. 2008). - Modify ordering infomation.(page 2) Revision 0.3 (Apr. 2008). - Update currently version “not supported burst mode＂ information. - Modify Typical Performance Characteristics without burst mode (page 5)

settop box block diagram

Abstract: 16QAM modulation qpsk modulation transmitter BCM3037 16 QAM Transmitter block diagram 16-QAM qpsk modulator chip dqpsk modulation transmitter QPSK-16/QAM-Modulator differential encoding in qam
Contextual Info: BCM3037 BCM3037 QAMLINK® UNIVERSAL BURST MODULATOR SUMMARY OF BENEFITS FEATURES • The Broadcom BCM3037 is a universal QPSK/QAM burst • A high-performance, integrated solution for upstream transmitter for DOCSIS/EuroDOCSIS applications • DOCSIS/EuroDOCSIS, IEEE 802.14, DAVIC and DVBcompliant

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

VAX-11

Abstract: PLCC 68 intel package dimensions 270917 w1a31 intel core i7 processors their registers in term of 32-bit mode
Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

Contextual Info: in te i 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz ■ 512-Byte On-Chip Instruction Cache — Direct Mapped

T7 DIODE

Contextual Info: inttJ PBßyiiflOMÄlHV 80960SA EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 20 MIPS* Burst Execution at 20 MHz — 7.5 MIPS Sustained Execution at 20 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

BCM3142

Abstract: BCM3216 Universal burst receiver QAM burst qpsk 1.28 mbps 12-Channel Mixer docsis 3.0 processor 94992
Contextual Info: BCM3142 Brief 12-CHANNEL UNIVERSAL ADVANCED TDMA/SCDMA PHY-LAYER BURST RECEIVER SUMMARY OF BENEFITS FEATURES • The BCM3142 is a universal headend advanced TDMA and SCDMA physical layer QPSK/QAM burst receiver. • Presents a high-performance, integrated solution for upstream demodulation in

FIR 3D 41

Abstract: burst qpsk 1.28 mbps RSSI stel-9244 Transistor FIR 3D 41 STEL-1108 STEL 320 tas 5612 STEL-9244A Stanford Telecom
Contextual Info: STEL-9244 Data Sheet STEL-9244 5 - 40 MHz QPSK Burst Receiver R Key Features • Burst QPSK demodulation ■ Data rate is 2.56 Mbps ■ Tunable 5 - 40 MHz RF input frequency for system flexibility ■ Fast acquisition time to minimize channel overhead; short

n80960sb

Contextual Info: in tj 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS • High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz ■ Built-In Interrupt Controller — 4 Direct Interrupt Pins

Contextual Info: AK2394 Burst Mode Controller for PHS Description The AK2394 is a TDM A/TDD Burst Mode Controller for Personal Handy phone System in Japan. The AK2394 consists of an ADPCM Interface, a Processor Interface, a Multiport Memory, a Transmit Logic, a Receive Logic, a Timing function, a Serial Interface and a

VAX-11

Abstract: 272207
Contextual Info: in t t J P ß m oM ow A nv 80960SB EMBEDDED 32-BIT MICROPROCESSOR WITH 16-BIT BURST DATA BUS High-Performance Embedded Architecture — 16 MIPS* Burst Execution at 16 MHz — 5 MIPS Sustained Execution at 16 MHz 512-Byte On-Chip Instruction Cache — Direct Mapped

c code for golay coding

Abstract: interleaver RJ-010 Block Interleaver circuitry Interleaver remote control encoder decoder encoder rc
Contextual Info: RJ-010 ERROR CORRECTOR FEATURES n On-chip encoder and decoder for full-duplex transmission n Corrects up to three random errors per 24-bit frame n Corrects up to a 9-bit error burst per 72-bit frame n Random errors or burst error correction modes are user-selectable